{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,19]],"date-time":"2026-05-19T15:33:41Z","timestamp":1779204821962,"version":"3.51.4"},"publisher-location":"Cham","reference-count":20,"publisher":"Springer Nature Switzerland","isbn-type":[{"value":"9783031783791","type":"print"},{"value":"9783031783807","type":"electronic"}],"license":[{"start":{"date-parts":[[2025,1,1]],"date-time":"2025-01-01T00:00:00Z","timestamp":1735689600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2025,1,1]],"date-time":"2025-01-01T00:00:00Z","timestamp":1735689600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025]]},"DOI":"10.1007\/978-3-031-78380-7_12","type":"book-chapter","created":{"date-parts":[[2025,1,27]],"date-time":"2025-01-27T15:50:58Z","timestamp":1737993058000},"page":"139-151","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":2,"title":["Plan Your Defense: A Comparative Analysis of\u00a0Leakage Detection Methods on\u00a0RISC-V Cores"],"prefix":"10.1007","author":[{"given":"Konstantina","family":"Miteloudi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Asmita","family":"Adhikary","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Niels","family":"van Drueten","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lejla","family":"Batina","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ileana","family":"Buhan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2025,1,28]]},"reference":[{"key":"12_CR1","doi-asserted-by":"publisher","unstructured":"Althoff, A., et al.: Hiding intermittent information leakage with architectural support for blinking. In: 45th ACM\/IEEE Annual International Symposium on Computer Architecture, ISCA, Los Angeles, CA, USA, pp. 638\u2013649 (2018). https:\/\/doi.org\/10.1109\/ISCA.2018.00059","DOI":"10.1109\/ISCA.2018.00059"},{"key":"12_CR2","doi-asserted-by":"publisher","unstructured":"Arora, V., Buhan, I., Perin, G., Picek, S.: A tale of two boards: on the influence of microarchitecture on side-channel leakage. In: Grosso, V., P\u00f6ppelmann, T. (eds.) CARDIS 2021. LNCS, vol. 13173, pp. 80\u201396. Springer, Cham (2021). https:\/\/doi.org\/10.1007\/978-3-030-97348-3_5","DOI":"10.1007\/978-3-030-97348-3_5"},{"key":"12_CR3","doi-asserted-by":"publisher","unstructured":"Bloem, R., Gigerl, B., Gourjon, M., Hadzic, V., Mangard, S., Primas, R.: Power contracts: provably complete power leakage models for processors. In: Conference on Computer and Communications Security, CCS , Los Angeles, CA, USA, pp. 381\u2013395. ACM (2022). https:\/\/doi.org\/10.1145\/3548606.3560600","DOI":"10.1145\/3548606.3560600"},{"key":"12_CR4","doi-asserted-by":"publisher","unstructured":"Buhan, I., Batina, L., Yarom, Y., Schaumont, P.: SoK: design tools for side-channel-aware implementations. In: ASIA CCS 2022: ACM Asia Conference on Computer and Communications Security, Nagasaki, Japan, pp. 756\u2013770. ACM (2022). https:\/\/doi.org\/10.1145\/3488932.3517415","DOI":"10.1145\/3488932.3517415"},{"key":"12_CR5","doi-asserted-by":"publisher","unstructured":"Demme, J., Martin, R., Waksman, A., Sethumadhavan, S.: Side-channel vulnerability factor: a metric for measuring information leakage. In: 39th International Symposium on Computer Architecture (ISCA), pp. 106\u2013117 (2012). https:\/\/doi.org\/10.1109\/ISCA.2012.6237010","DOI":"10.1109\/ISCA.2012.6237010"},{"key":"12_CR6","doi-asserted-by":"publisher","unstructured":"F, M.A.K., Ganesan, V., Bodduna, R., Rebeiro, C.: PARAM: a microprocessor hardened for power side-channel attack resistance. In: International Symposium on Hardware Oriented Security and Trust, HOST, San Jose, CA, USA, pp. 23\u201334. IEEE (2020). https:\/\/doi.org\/10.1109\/HOST45689.2020.9300263","DOI":"10.1109\/HOST45689.2020.9300263"},{"key":"12_CR7","doi-asserted-by":"publisher","unstructured":"Gao, S., Gro\u00dfsch\u00e4dl, J., Marshall, B., Page, D., Pham, T.H., Regazzoni, F.: An instruction set extension to support software-based masking. IACR Trans. Cryptogr. Hardw. Embed. Syst., 283\u2013325 (2021). https:\/\/doi.org\/10.46586\/tches.v2021.i4.283-325","DOI":"10.46586\/tches.v2021.i4.283-325"},{"key":"12_CR8","unstructured":"Gigerl, B., Hadzic, V., Primas, R., Mangard, S., Bloem, R.: COCO: co-design and co-verification of masked software implementations on CPUs. In: 30th USENIX Security Symposium, USENIX, pp. 1469\u20131468 (2021)"},{"key":"12_CR9","unstructured":"Gilbert\u00a0Goodwill, B.J., Jaffe, J., Rohatgi, P., et\u00a0al.: A testing methodology for side-channel resistance validation. In: NIST Non-invasive Attack Testing Workshop, vol.\u00a07, pp. 115\u2013136 (2011)"},{"key":"12_CR10","doi-asserted-by":"publisher","unstructured":"He, M.T., Park, J., Nahiyan, A., Vassilev, A., Jin, Y., Tehranipoor, M.M.: RTL-PSC: automated power side-channel leakage assessment at register-transfer level. In: 37th IEEE VLSI Test Symposium, VTS Monterey, CA, USA, pp.\u00a01\u20136 (2019). https:\/\/doi.org\/10.1109\/VTS.2019.8758600","DOI":"10.1109\/VTS.2019.8758600"},{"key":"12_CR11","doi-asserted-by":"publisher","unstructured":"Kiaei, P., Schaumont, P.: SoC root canal! Root cause analysis of power side-channel leakage in system-on-chip designs. IACR Trans. Cryptogr. Hardw. Embed. Syst., 751\u2013773 (2022). https:\/\/doi.org\/10.46586\/tches.v2022.i4.751-773","DOI":"10.46586\/tches.v2022.i4.751-773"},{"key":"12_CR12","doi-asserted-by":"publisher","unstructured":"Lakshmy, A.V., Rebeiro, C., Bhunia, S.: FORTIFY: analytical pre-silicon side-channel characterization of digital designs. In: 27th Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 660\u2013665. IEEE (2022). https:\/\/doi.org\/10.1109\/ASP-DAC52403.2022.9712551","DOI":"10.1109\/ASP-DAC52403.2022.9712551"},{"key":"12_CR13","unstructured":"lowRISC: Lowrisc\/ibex-demo-system: A demo system for ibex. https:\/\/github.com\/lowRISC\/ibex-demo-system"},{"key":"12_CR14","doi-asserted-by":"publisher","unstructured":"Marshall, B., Page, D., Webb, J.: MIRACLE: micro-architectural leakage evaluation a study of micro-architectural power leakage across many devices. IACR Trans. Cryptogr. Hardw. Embed. Syst., 175\u2013220 (2022). https:\/\/doi.org\/10.46586\/TCHES.V2022.I1.175-220","DOI":"10.46586\/TCHES.V2022.I1.175-220"},{"key":"12_CR15","doi-asserted-by":"publisher","unstructured":"Mulder, E.D., Gummalla, S., Hutter, M.: Protecting RISC-V against side-channel attacks. In: Proceedings of the 56th Annual Design Automation Conference 2019, DAC, Las Vegas, NV, USA, p.\u00a045 (2019). https:\/\/doi.org\/10.1145\/3316781.3323485","DOI":"10.1145\/3316781.3323485"},{"key":"12_CR16","doi-asserted-by":"publisher","unstructured":"Pham, T.H., Marshall, B., Fell, A., Lam, S., Page, D.: XDIVINSA: extended diversifying instruction agent to mitigate power side-channel leakage. In: 32nd IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP, pp. 179\u2013186 (2021). https:\/\/doi.org\/10.1109\/ASAP52443.2021.00034","DOI":"10.1109\/ASAP52443.2021.00034"},{"key":"12_CR17","unstructured":"SHAKTI: Family of processors (2021). https:\/\/shakti.org.in\/processors.html"},{"key":"12_CR18","doi-asserted-by":"publisher","unstructured":"SLPSK, P., Vairam, P.K., Rebeiro, C., Kamakoti, V.: Karna: a gate-sizing based security aware EDA flow for improved power side-channel attack protection. In: Proceedings of the International Conference on Computer-Aided Design, pp.\u00a01\u20138 (2019). https:\/\/doi.org\/10.1109\/ICCAD45719.2019.8942173","DOI":"10.1109\/ICCAD45719.2019.8942173"},{"key":"12_CR19","doi-asserted-by":"publisher","unstructured":"Yao, Y., Kathuria, T., Ege, B., Schaumont, P.: Architecture correlation analysis (ACA): identifying the source of side-channel leakage at gate-level. In: International Symposium on Hardware Oriented Security and Trust, HOST, San Jose, CA, USA, pp. 188\u2013196. IEEE (2020). https:\/\/doi.org\/10.1109\/HOST45689.2020.9300271","DOI":"10.1109\/HOST45689.2020.9300271"},{"key":"12_CR20","doi-asserted-by":"publisher","unstructured":"Zhang, T., Liu, F., Chen, S., Lee, R.B.: Side channel vulnerability metrics: the promise and the pitfalls. In: HASP 2013, The Second Workshop on Hardware and Architectural Support for Security and Privacy, Tel-Aviv, Israel, p.\u00a02. ACM (2013). https:\/\/doi.org\/10.1145\/2487726.2487728","DOI":"10.1145\/2487726.2487728"}],"container-title":["Lecture Notes in Computer Science","Embedded Computer Systems: Architectures, Modeling, and Simulation"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-031-78380-7_12","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,27]],"date-time":"2025-01-27T15:51:01Z","timestamp":1737993061000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-031-78380-7_12"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025]]},"ISBN":["9783031783791","9783031783807"],"references-count":20,"URL":"https:\/\/doi.org\/10.1007\/978-3-031-78380-7_12","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"value":"0302-9743","type":"print"},{"value":"1611-3349","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025]]},"assertion":[{"value":"28 January 2025","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"SAMOS","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Samos","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Greece","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2024","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"30 June 2024","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"5 July 2024","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"24","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"samos2024","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"https:\/\/samos-conference.com\/wp\/","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}}]}}