{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,5]],"date-time":"2025-04-05T04:21:17Z","timestamp":1743826877041,"version":"3.40.3"},"publisher-location":"Cham","reference-count":32,"publisher":"Springer Nature Switzerland","isbn-type":[{"value":"9783031879944","type":"print"},{"value":"9783031879951","type":"electronic"}],"license":[{"start":{"date-parts":[[2025,1,1]],"date-time":"2025-01-01T00:00:00Z","timestamp":1735689600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2025,1,1]],"date-time":"2025-01-01T00:00:00Z","timestamp":1735689600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025]]},"DOI":"10.1007\/978-3-031-87995-1_6","type":"book-chapter","created":{"date-parts":[[2025,4,4]],"date-time":"2025-04-04T19:20:11Z","timestamp":1743794411000},"page":"88-105","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["ROBoost: A Study of\u00a0FPGA Logic-Based Power-Wasting Primitives"],"prefix":"10.1007","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-0720-1342","authenticated-orcid":false,"given":"Dina G.","family":"Mahmoud","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Simone","family":"Andreani","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2289-3722","authenticated-orcid":false,"given":"Vincent","family":"Lenders","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5649-5020","authenticated-orcid":false,"given":"Mirjana","family":"Stojilovi\u0107","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2025,4,4]]},"reference":[{"key":"6_CR1","doi-asserted-by":"crossref","unstructured":"Alrahis, L., Nassar, H., Krautter, J., Gnad, D., Bauer, L., Henkel, J., Tahoori, M.: MaliGNNoma: GNN-based malicious circuit classifier for secure cloud FPGAs. arXiv, March 2024. arXiv:2403.01860 [cs]","DOI":"10.1109\/HOST55342.2024.10545411"},{"key":"6_CR2","unstructured":"AWS EC2 FPGA HDK+SDK errata (2019). https:\/\/github.com\/aws\/aws-fpga\/blob\/master\/ERRATA.md"},{"key":"6_CR3","unstructured":"FPGA-based Amazon EC2 F1 computing instances (2022). https:\/\/aws.amazon.com\/ec2\/instance-types\/f1\/"},{"key":"6_CR4","unstructured":"66906 - UltraScale soft error mitigation (SEM) IP - [DRC 23-20] rule violation (PDCN-1569) LUT equation term check, September 2021. https:\/\/support.xilinx.com\/s\/article\/66906?language=en_US"},{"key":"6_CR5","doi-asserted-by":"crossref","unstructured":"Amer, H.H.: Behavior of memory elements in the presence of power supply disturbances. In: 34th Annual Spring Reliability Symposium, \u201cReliability - Investing in the Future, pp. 45\u201351. Boxborough, MA, USA, April 1996","DOI":"10.1109\/SRS.1996.618958"},{"key":"6_CR6","doi-asserted-by":"crossref","unstructured":"Chen, C.H., Bowman, K., Augustine, C., Zhang, Z., Tschanz, J.: Minimum supply voltage for sequential logic circuits in a 22nm technology. In: International Symposium on Low Power Electronics and Design, pp. 181\u2013186. Beijing, China, September 2013","DOI":"10.1109\/ISLPED.2013.6629291"},{"key":"6_CR7","unstructured":"Garc\u00eda, A.D.G., P\u00e9rez, L.F.G., Acu\u00f1a, R.F.: Power consumption management on FPGAs. In: 15th International Conference on Electronics, Communications and Computers, pp. 240\u2014245, February 2005"},{"key":"6_CR8","unstructured":"Genesys ZU: Zynq UltraScale+ MPSoC development board (2022). https:\/\/digilent.com\/reference\/programmable-logic\/genesys-zu\/reference-manual"},{"key":"6_CR9","doi-asserted-by":"crossref","unstructured":"Giechaskiel, I., Rasmussen, K.B., Szefer, J.: Measuring long wire leakage with ring oscillators in cloud FPGAs. In: 29th International Conference on Field-Programmable Logic and Applications, pp. 45\u201350. Barcelona, Spain, September 2019","DOI":"10.1109\/FPL.2019.00017"},{"key":"6_CR10","doi-asserted-by":"crossref","unstructured":"Glamo\u010danin, O., Coulon, L., Regazzoni, F., Stojilovi\u0107, M.: Are cloud FPGAs really vulnerable to power analysis attacks? In: Design, Automation & Test in Europe Conference & Exhibition (DATE), pp.\u00a01\u20134. Grenoble, France, March 2020","DOI":"10.23919\/DATE48585.2020.9116481"},{"key":"6_CR11","doi-asserted-by":"crossref","unstructured":"Glamo\u010danin, O., Kosti\u0107, A., Kosti\u0107, S., Stojilovi\u0107, M.: Active wire fences for multitenant FPGAs. In: DDECS, pp. 13\u201320, May 2023","DOI":"10.1109\/DDECS57882.2023.10138941"},{"key":"6_CR12","doi-asserted-by":"crossref","unstructured":"Gnad, D.R.E., Oboril, F., Tahoori, M.B.: Voltage drop-based fault attacks on FPGAs using valid bitstreams. In: FPL, pp.\u00a01\u20137. Ghent, Belgium, September 2017","DOI":"10.23919\/FPL.2017.8056840"},{"key":"6_CR13","doi-asserted-by":"crossref","unstructured":"Gupta, M.S., Oatley, J.L., Joseph, R., Wei, G.Y., Brooks, D.M.: Understanding voltage variations in chip multiprocessors using a distributed power-delivery network. In: Design, Automation & Test in Europe Conference & Exhibition (DATE), pp.\u00a01\u20136. Nice, France, April 2007","DOI":"10.1109\/DATE.2007.364663"},{"issue":"3","key":"6_CR14","doi-asserted-by":"crossref","first-page":"441","DOI":"10.46586\/tches.v2021.i3.441-464","volume":"2021","author":"T La","year":"2021","unstructured":"La, T., Pham, K., Powell, J., Koch, D.: Denial-of-Service on FPGA-based cloud infrastructures - attack and defense. IACR Trans. Cryptographic Hardware Embedded Syst. 2021(3), 441\u2013464 (2021)","journal-title":"IACR Trans. Cryptographic Hardware Embedded Syst."},{"key":"6_CR15","doi-asserted-by":"crossref","unstructured":"La, T.M., Matas, K., Grunchevski, N., Pham, K.D., Koch, D.: FPGADefender: malicious self-oscillator scanning for Xilinx UltraScale + FPGAs. ACM Trans. Reconfigurable Technol. Syst. 13(3), 15:1\u201315:31 (2020)","DOI":"10.1145\/3402937"},{"key":"6_CR16","doi-asserted-by":"publisher","DOI":"10.5281\/zenodo.14840696","author":"DG Mahmoud","year":"2025","unstructured":"Mahmoud, D.G., Andreani, S., Lenders, V., Stojilovi\u0107, M.: ROBoost: a study of FPGA logic-based power-wasting primitives. Artifacts (2025). https:\/\/doi.org\/10.5281\/zenodo.14840696","journal-title":"Artifacts"},{"key":"6_CR17","doi-asserted-by":"crossref","first-page":"134199","DOI":"10.1109\/ACCESS.2022.3231753","volume":"10","author":"DG Mahmoud","year":"2022","unstructured":"Mahmoud, D.G., Dervishi, D., Hussein, S., Lenders, V., Stojilovi\u0107, M.: DFAulted: Analyzing and exploiting CPU software faults caused by FPGA-driven undervolting attacks. IEEE Access 10, 134199\u2013216 (2022)","journal-title":"IEEE Access"},{"key":"6_CR18","doi-asserted-by":"crossref","unstructured":"Mahmoud, D.G., Hussein, S., Lenders, V., Stojilovi\u0107, M.: FPGA-to-CPU undervolting attacks. In: Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 999\u20131004, March 2022","DOI":"10.23919\/DATE54114.2022.9774663"},{"key":"6_CR19","doi-asserted-by":"crossref","unstructured":"Mahmoud, D.G., Shokry, B., Lenders, V., Hu, W., Stojilovi\u0107, M.: X-Attack 2.0: the risk of power wasters and satisfiability don\u2019t-care hardware trojans to shared cloud FPGAs. IEEE Access 12, 8983\u20139011 (2024)","DOI":"10.1109\/ACCESS.2024.3353134"},{"key":"6_CR20","doi-asserted-by":"crossref","unstructured":"Matas, K., La, T.M., Pham, K.D., Koch, D.: Power-hammering through glitch amplification - attacks and mitigation. In: 28th Symposium on Field-Programmable Custom Computing Machines. pp. 65\u201369. Fayetteville, AR, USA, May 2020","DOI":"10.1109\/FCCM48280.2020.00018"},{"key":"6_CR21","doi-asserted-by":"crossref","unstructured":"Moini, S., Deric, A., Li, X., Provelengios, G., Burleson, W., Tessier, R., Holcomb, D.: Voltage sensor implementations for remote power attacks on FPGAs. ACM Trans. Reconfigurable Technol. Syst. 16(1) (2022)","DOI":"10.1145\/3555048"},{"key":"6_CR22","unstructured":"Pant, S.: Design and analysis of power distribution networks in VLSI Circuits. Ph.D. thesis, The University of Michigan (2008). https:\/\/deepblue.lib.umich.edu\/bitstream\/handle\/2027.42\/58508\/spant_1.pdf%3Fsequence%3D1"},{"key":"6_CR23","doi-asserted-by":"crossref","unstructured":"Provelengios, G., Holcomb, D., Tessier, R.: Power wasting circuits for cloud FPGA attacks. In: 30th International Conference on Field-Programmable Logic and Applications, pp. 231\u201335. Gothenburg, Sweden, August 2020","DOI":"10.1109\/FPL50879.2020.00046"},{"key":"6_CR24","unstructured":"Digilent reference for PYNQ-Z1. https:\/\/digilent.com\/reference\/programmable-logic\/pynq-z1\/start"},{"issue":"6","key":"6_CR25","doi-asserted-by":"crossref","first-page":"1114","DOI":"10.1109\/TCAD.2006.885834","volume":"26","author":"E Salman","year":"2007","unstructured":"Salman, E., Dasdan, A., Taraporevala, F., Kucukcakar, K., Friedman, E.G.: Exploiting setup-hold-time interdependence in static timing analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(6), 1114\u201325 (2007)","journal-title":"IEEE Trans. Comput. Aided Des. Integr. Circuits Syst."},{"issue":"2","key":"6_CR26","doi-asserted-by":"crossref","first-page":"543","DOI":"10.46586\/tches.v2023.i2.543-567","volume":"2023","author":"D Spielmann","year":"2023","unstructured":"Spielmann, D., Glamo\u010danin, O., Stojilovi\u0107, M.: RDS: FPGA routing delay sensors for effective remote power analysis attacks. IACR Trans. Cryptographic Hardware Embedded Syst. 2023(2), 543\u2013567 (2023)","journal-title":"IACR Trans. Cryptographic Hardware Embedded Syst."},{"issue":"12","key":"6_CR27","doi-asserted-by":"crossref","first-page":"1548","DOI":"10.1109\/JPROC.2023.3330729","volume":"111","author":"M Stojilovi\u0107","year":"2023","unstructured":"Stojilovi\u0107, M., Rasmussen, K., Regazzoni, F., Tahoori, M.B., Tessier, R.: A visionary look at the security of reconfigurable cloud computing. Proc. IEEE 111(12), 1548\u201371 (2023)","journal-title":"Proc. IEEE"},{"key":"6_CR28","unstructured":"UltraScale architecture system monitor user guide, September 2021"},{"key":"6_CR29","unstructured":"Xilinx Inc.: 7 series FPGAs configurable logic block user guide (UG474), September 2016"},{"key":"6_CR30","unstructured":"Xilinx Inc.: UltraScale architecture configurable logic block user guide (UG574), February 2017"},{"key":"6_CR31","unstructured":"Xilinx Inc.: Zynq-7000 SoC: DC and AC switching characteristics (DS187), December 2020"},{"key":"6_CR32","doi-asserted-by":"crossref","unstructured":"Zhao, M., Suh, G.E.: FPGA-based remote power side-channel attacks. In: IEEE Symposium on Security and Privacy (SP), pp. 229\u2013244. San Francisco, CA, USA, May 2018","DOI":"10.1109\/SP.2018.00049"}],"container-title":["Lecture Notes in Computer Science","Applied Reconfigurable Computing. Architectures, Tools, and Applications"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-031-87995-1_6","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,4,4]],"date-time":"2025-04-04T19:20:28Z","timestamp":1743794428000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-031-87995-1_6"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025]]},"ISBN":["9783031879944","9783031879951"],"references-count":32,"URL":"https:\/\/doi.org\/10.1007\/978-3-031-87995-1_6","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"value":"0302-9743","type":"print"},{"value":"1611-3349","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025]]},"assertion":[{"value":"4 April 2025","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"ARC","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"International Symposium on Applied Reconfigurable Computing","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Seville","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Spain","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2025","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"9 April 2025","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"11 April 2025","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"21","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"arc2025","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"https:\/\/arc2025.org\/","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}}]}}