{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,10]],"date-time":"2025-06-10T04:03:21Z","timestamp":1749528201499,"version":"3.41.0"},"publisher-location":"Cham","reference-count":21,"publisher":"Springer Nature Switzerland","isbn-type":[{"value":"9783031902024","type":"print"},{"value":"9783031902031","type":"electronic"}],"license":[{"start":{"date-parts":[[2025,1,1]],"date-time":"2025-01-01T00:00:00Z","timestamp":1735689600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2025,1,1]],"date-time":"2025-01-01T00:00:00Z","timestamp":1735689600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025]]},"DOI":"10.1007\/978-3-031-90203-1_53","type":"book-chapter","created":{"date-parts":[[2025,6,9]],"date-time":"2025-06-09T15:49:17Z","timestamp":1749484157000},"page":"431-442","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Pre-scheduling of\u00a0Affine Loops for\u00a0HLS Pipelining"],"prefix":"10.1007","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-8202-1627","authenticated-orcid":false,"given":"Serena","family":"Curzel","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2061-0802","authenticated-orcid":false,"given":"Sofija","family":"Jovic","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8675-6703","authenticated-orcid":false,"given":"Michele","family":"Fiorito","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9452-120X","authenticated-orcid":false,"given":"Antonino","family":"Tumeo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0301-4419","authenticated-orcid":false,"given":"Fabrizio","family":"Ferrandi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2025,6,10]]},"reference":[{"issue":"5","key":"53_CR1","doi-asserted-by":"publisher","first-page":"78","DOI":"10.1109\/MM.2022.3178580","volume":"42","author":"N Bohm Agostini","year":"2022","unstructured":"Bohm Agostini, N., Curzel, S., Zhang, J.J., Limaye, A., Tan, C., Amatya, V., et al.: Bridging Python to silicon: the SODA toolchain. IEEE Micro 42(5), 78\u201388 (2022)","journal-title":"IEEE Micro"},{"issue":"11","key":"53_CR2","doi-asserted-by":"publisher","first-page":"4229","DOI":"10.1109\/TCAD.2020.3012866","volume":"39","author":"S Derrien","year":"2020","unstructured":"Derrien, S., Marty, T., Rokicki, S., Yuki, T.: Toward speculative loop pipelining for high-level synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(11), 4229\u20134239 (2020)","journal-title":"IEEE Trans. Comput. Aided Des. Integr. Circuits Syst."},{"key":"53_CR3","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"80","DOI":"10.1007\/978-3-540-92990-1_8","volume-title":"High Performance Embedded Architectures and Compilers","author":"M Fellahi","year":"2009","unstructured":"Fellahi, M., Cohen, A.: Software pipelining in nested loops with prolog-epilog merging. In: Seznec, A., Emer, J., O\u2019Boyle, M., Martonosi, M., Ungerer, T. (eds.) HiPEAC 2009. LNCS, vol. 5409, pp. 80\u201394. Springer, Heidelberg (2009). https:\/\/doi.org\/10.1007\/978-3-540-92990-1_8"},{"key":"53_CR4","doi-asserted-by":"crossref","unstructured":"Ferrandi, F., Castellana, V.G., Curzel, S., Fezzardi, P., Fiorito, M., Lattuada, M., et\u00a0al.: Bambu: an open-source research framework for the high-level synthesis of complex applications. In: DAC 2021: 58th ACM\/IEEE Design Automation Conference (2021)","DOI":"10.1109\/DAC18074.2021.9586110"},{"key":"53_CR5","doi-asserted-by":"publisher","unstructured":"Lam, M.S.: Software pipelining. In: A Systolic Array Optimizing Compiler. The Kluwer International Series in Engineering and Computer Science, vol. 64, pp. 83\u2013124. Springer, Boston (1989). https:\/\/doi.org\/10.1007\/978-1-4613-1705-0_5","DOI":"10.1007\/978-1-4613-1705-0_5"},{"key":"53_CR6","doi-asserted-by":"crossref","unstructured":"Lattner, C., Amini, M., Bondhugula, U., Cohen, A., Davis, A., Pienaar, J., et\u00a0al.: MLIR: scaling Compiler Infrastructure for Domain Specific Computation. In: CGO 2021: IEEE\/ACM International Symposium on Code Generation and Optimization, pp. 2\u201314. IEEE (2021)","DOI":"10.1109\/CGO51591.2021.9370308"},{"key":"53_CR7","unstructured":"Li, P., Pouchet, L.N., Cong, J.: Throughput optimization for high-level synthesis using resource constraints. In: IMPACT 2014: International Workshop on Polyhedral Compilation Techniques (2014)"},{"key":"53_CR8","doi-asserted-by":"crossref","unstructured":"Liang, G.M., Yuan, C.Y., Yuan, M.S., Chen, T.L., Chen, K.H., Lee, J.K.: The support of MLIR HLS adaptor for LLVM IR. In: Workshop Proceedings of the 51st International Conference on Parallel Processing (2023)","DOI":"10.1145\/3547276.3548515"},{"issue":"9","key":"53_CR9","doi-asserted-by":"publisher","first-page":"1802","DOI":"10.1109\/TCAD.2017.2783363","volume":"37","author":"J Liu","year":"2017","unstructured":"Liu, J., Wickerson, J., Bayliss, S., Constantinides, G.A.: Polyhedral-based dynamic loop pipelining for high-level synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(9), 1802\u20131815 (2017)","journal-title":"IEEE Trans. Comput. Aided Des. Integr. Circuits Syst."},{"key":"53_CR10","doi-asserted-by":"crossref","unstructured":"Moses, W.S., Chelini, L., Zhao, R., Zinenko, O.: Polygeist: Raising c to polyhedral MLIR. In: PACT 2021: 30th International Conference on Parallel Architectures and Compilation Techniques, pp. 45\u201359 (2021)","DOI":"10.1109\/PACT52795.2021.00011"},{"key":"53_CR11","doi-asserted-by":"crossref","unstructured":"Oppermann, J., Koch, A., Reuter-Oppermann, M., Sinnen, O.: ILP-based Modulo Scheduling for High-Level Synthesis. In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES), pp. 1\u201310 (2016)","DOI":"10.1145\/2968455.2968512"},{"key":"53_CR12","doi-asserted-by":"crossref","unstructured":"Pilato, C., B\u00f6hm, S., Brocheton, F., Castrill\u00f3n, J., Cevasco, R., Cima, V., et\u00a0al.: EVEREST: a design environment for extreme-scale big data analytics on heterogeneous platforms. In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2021, Grenoble, France, 1-5 February 2021, pp. 1320\u20131325. IEEE (2021)","DOI":"10.23919\/DATE51398.2021.9473940"},{"key":"53_CR13","doi-asserted-by":"crossref","unstructured":"Pouchet, L.N., Zhang, P., Sadayappan, P., Cong, J.: Polyhedral-Based Data Reuse Optimization for Configurable Computing. In: Proceedings of the ACM\/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), pp. 29\u201338 (2013)","DOI":"10.1145\/2435264.2435273"},{"key":"#cr-split#-53_CR14.1","unstructured":"Sittel, P., Oppermann, J., Kumm, M., Koch, A., Zipf, P.: HatScheT: a contribution to agile HLS. In: FSP Workshop 2018"},{"key":"#cr-split#-53_CR14.2","unstructured":"Fifth International Workshop on FPGAs for Software Programmers, pp.\u00a01-8. VDE (2018)"},{"key":"53_CR15","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"336","DOI":"10.1007\/978-3-540-27866-5_43","volume-title":"Euro-Par 2004 Parallel Processing","author":"A Stoutchinin","year":"2004","unstructured":"Stoutchinin, A., Gao, G.: If-conversion in SSA form. In: Danelutto, M., Vanneschi, M., Laforenza, D. (eds.) Euro-Par 2004. LNCS, vol. 3149, pp. 336\u2013345. Springer, Heidelberg (2004). https:\/\/doi.org\/10.1007\/978-3-540-27866-5_43"},{"key":"53_CR16","unstructured":"Urbach, M., Petersen, M.B.: HLS from PyTorch to System Verilog with MLIR and CIRCT (2022). In: 2nd Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE) (2022)"},{"key":"53_CR17","doi-asserted-by":"crossref","unstructured":"Ye, H., et al.: ScaleHLS: a new scalable high-level synthesis framework on multi-level intermediate representation. In: 2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA), pp. 741\u2013755. IEEE (2022)","DOI":"10.1109\/HPCA53966.2022.00060"},{"key":"53_CR18","doi-asserted-by":"crossref","unstructured":"Zhao, R., Cheng, J., Luk, W., Constantinides, G.A.: POLSCA: Polyhedral High-Level Synthesis with Compiler Transformations. In: International Conference on Field-Programmable Logic and Applications (FPL) (2022)","DOI":"10.1109\/FPL57034.2022.00044"},{"key":"53_CR19","doi-asserted-by":"crossref","unstructured":"Zuo, W., Li, P., Chen, D., Pouchet, L.N., Zhong, S., Cong, J.: Improving polyhedral code generation for high-level synthesis. In: CODES+ISSS 2013: International Conference on Hardware\/Software Codesign and System Synthesis, pp. 1\u201310 (2013)","DOI":"10.1109\/CODES-ISSS.2013.6659002"},{"key":"53_CR20","doi-asserted-by":"crossref","unstructured":"Zuo, W., Liang, Y., Li, P., Rupnow, K., Chen, D., Cong, J.: Improving high level synthesis optimization opportunity through polyhedral transformations. In: FPGA 2013: Proceedings of the ACM\/SIGDA International Symposium on Field Programmable Gate Arrays, pp. 9\u201318 (2013)","DOI":"10.1145\/2435264.2435271"}],"container-title":["Lecture Notes in Computer Science","Euro-Par 2024: Parallel Processing Workshops"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-031-90203-1_53","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,9]],"date-time":"2025-06-09T15:49:24Z","timestamp":1749484164000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-031-90203-1_53"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025]]},"ISBN":["9783031902024","9783031902031"],"references-count":21,"URL":"https:\/\/doi.org\/10.1007\/978-3-031-90203-1_53","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"value":"0302-9743","type":"print"},{"value":"1611-3349","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025]]},"assertion":[{"value":"10 June 2025","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"Euro-Par","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"European Conference on Parallel Processing","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Madrid","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Spain","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2024","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"26 August 2024","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"30 August 2024","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"30","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"europar2024","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"https:\/\/2024.euro-par.org\/","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}}]}}