{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,10]],"date-time":"2025-07-10T10:10:08Z","timestamp":1752142208079,"version":"3.41.2"},"publisher-location":"Cham","reference-count":41,"publisher":"Springer Nature Switzerland","isbn-type":[{"value":"9783031976223","type":"print"},{"value":"9783031976230","type":"electronic"}],"license":[{"start":{"date-parts":[[2025,1,1]],"date-time":"2025-01-01T00:00:00Z","timestamp":1735689600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2025,1,1]],"date-time":"2025-01-01T00:00:00Z","timestamp":1735689600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025]]},"DOI":"10.1007\/978-3-031-97623-0_18","type":"book-chapter","created":{"date-parts":[[2025,7,10]],"date-time":"2025-07-10T09:30:27Z","timestamp":1752139827000},"page":"297-315","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["FAULTLESS: Flexible and\u00a0Transparent Fault Protection for\u00a0Superscalar RISC-V Processors"],"prefix":"10.1007","author":[{"ORCID":"https:\/\/orcid.org\/0009-0007-0140-6802","authenticated-orcid":false,"given":"Moritz","family":"Waser","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0009-0004-5913-6452","authenticated-orcid":false,"given":"David","family":"Schrammel","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6462-8671","authenticated-orcid":false,"given":"Robert","family":"Schilling","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9650-8041","authenticated-orcid":false,"given":"Stefan","family":"Mangard","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2025,7,10]]},"reference":[{"key":"18_CR1","doi-asserted-by":"crossref","unstructured":"Baleani, M., et\u00a0al.: Fault-tolerant platforms for automotive safety-critical applications. In: CASES 2003 (2003)","DOI":"10.1145\/951710.951734"},{"key":"18_CR2","doi-asserted-by":"crossref","unstructured":"Barenghi, A., et\u00a0al.: Countermeasures against fault attacks on software implemented AES: effectiveness and cost. In: WESS 2010 (2010)","DOI":"10.1145\/1873548.1873555"},{"key":"18_CR3","doi-asserted-by":"crossref","unstructured":"Barry, T., et\u00a0al.: Compilation of a countermeasure against instruction-skip fault attacks. In: CS2@HiPEAC\u201991 (2016)","DOI":"10.1145\/2858930.2858931"},{"key":"18_CR4","doi-asserted-by":"crossref","unstructured":"Boneh, D., et\u00a0al.: On the importance of checking cryptographic protocols for faults (extended abstract). In: EUROCRYPT 1997 (1997)","DOI":"10.1007\/3-540-69053-0_4"},{"key":"18_CR5","doi-asserted-by":"crossref","unstructured":"Chen, Z., et\u00a0al.: SIMD-based soft error detection. In: CF 2016 (2016)","DOI":"10.1145\/2903150.2903170"},{"key":"18_CR6","doi-asserted-by":"crossref","unstructured":"Cojocar, L., et\u00a0al.: Instruction duplication: leaky and not too fault-tolerant! In: CARDIS 2017 (2017)","DOI":"10.1007\/978-3-319-75208-2_10"},{"key":"18_CR7","unstructured":"Digital, W.: RISC-V: high performance embedded SweRV core microarchitecture, performance and CHIPS alliance (2019). https:\/\/riscv.org\/wp-content\/uploads\/2019\/04\/RISC-V_SweRV_Roadshow-.pdf. Accessed 18 Aug 2023"},{"key":"18_CR8","doi-asserted-by":"crossref","unstructured":"Dobraunig, C., et\u00a0al.: SIFA: exploiting ineffective fault inductions on symmetric cryptography. IACR Trans. Cryptogr. Hardw. Embed. Syst. (2018)","DOI":"10.46586\/tches.v2018.i3.547-572"},{"key":"18_CR9","unstructured":"Franklin, M.: Incorporating fault tolerance in superscalar processors. In: HIPC 1996 (1996)"},{"key":"18_CR10","unstructured":"Free and Open Source Silicon Foundation: Embench: open benchmarks for embedded platforms (nd). https:\/\/github.com\/embench\/embench-iot\/. Accessed 13 Jan 2023"},{"key":"18_CR11","doi-asserted-by":"crossref","unstructured":"Gruss, D., et\u00a0al.: Rowhammer.js: a remote software-induced fault attack in JavaScript. In: DIMVA 2016 (2016)","DOI":"10.1007\/978-3-319-40667-1_15"},{"key":"18_CR12","doi-asserted-by":"crossref","unstructured":"Gupta, S., et\u00a0al.: SHAKTI-F: a fault tolerant microprocessor architecture. In: ATS 2015 (2015)","DOI":"10.1109\/ATS.2015.35"},{"key":"18_CR13","doi-asserted-by":"crossref","unstructured":"Hamming, R.W.: Error detecting and error correcting codes. Bell Syst. Tech. J. (1950)","DOI":"10.1002\/j.1538-7305.1950.tb00463.x"},{"key":"18_CR14","unstructured":"Infineon: 32-bit AURIX\u2122TriCore\u2122Microcontroller (nd). https:\/\/www.infineon.com\/cms\/de\/product\/microcontroller\/32-bit-tricore-microcontroller\/. Accessed 15 Apr 2024"},{"key":"18_CR15","doi-asserted-by":"crossref","unstructured":"Karaklajic, D., et\u00a0al.: Hardware designer\u2019s guide to fault attacks. IEEE Trans. Very Large Scale Integr. Syst. (2013)","DOI":"10.1109\/TVLSI.2012.2231707"},{"key":"18_CR16","doi-asserted-by":"crossref","unstructured":"Keller, A.M., Wirthlin, M.J.: The impact of terrestrial radiation on FPGAs in data centers. ACM Trans. Reconfigurable Technol. Syst. (2022)","DOI":"10.1145\/3457198"},{"key":"18_CR17","doi-asserted-by":"crossref","unstructured":"Kuvaiskii, D., et\u00a0al.: HAFT: hardware-assisted fault tolerance. In: EUROSYS 2016 (2016)","DOI":"10.1145\/2901318.2901339"},{"key":"18_CR18","doi-asserted-by":"crossref","unstructured":"Laurent, J., et\u00a0al.: Cross-layer analysis of software fault models and countermeasures against hardware fault attacks in a RISC-V processor. Microprocess. Microsyst. (2019)","DOI":"10.1016\/j.micpro.2019.102862"},{"key":"18_CR19","doi-asserted-by":"crossref","unstructured":"Luza, L.M., et\u00a0al.: Impact of atmospheric and space radiation on sensitive electronic devices. In: ETS 2022 (2022)","DOI":"10.1109\/ETS54262.2022.9810454"},{"key":"18_CR20","doi-asserted-by":"crossref","unstructured":"Lyons, R.E., Vanderkulk, W.: The use of triple-modular redundancy to improve computer reliability. IBM J. Res. Dev. (1962)","DOI":"10.1147\/rd.62.0200"},{"key":"18_CR21","doi-asserted-by":"crossref","unstructured":"Murdock, K., et\u00a0al.: Plundervolt: software-based fault injection attacks against intel SGX. In: S &P 2020 (2020)","DOI":"10.1109\/SP40000.2020.00057"},{"key":"18_CR22","doi-asserted-by":"crossref","unstructured":"Nicolescu, B., et\u00a0al.: Software detection mechanisms providing full coverage against single bit-flip faults. IEEE Trans. Nucl. Sci. (2004)","DOI":"10.1109\/TNS.2004.839110"},{"key":"18_CR23","unstructured":"NXP: S32K3 Microcontrollers for Automotive General Purpose (nd). https:\/\/www.nxp.com\/products\/processors-and-microcontrollers\/s32-automotive-platform\/s32k-auto-general-purpose-mcus\/s32k3-microcontrollers-for-automotive-general-purpose:S32K3. Accessed 15 Apr 2024"},{"key":"18_CR24","unstructured":"O\u2019Flynn, C.: BAM BAM!! on reliability of EMFI for in-situ automotive ECU attacks. IACR Cryptology ePrint Archive (2020)"},{"key":"18_CR25","doi-asserted-by":"crossref","unstructured":"Oh, N., et\u00a0al.: Error detection by duplicated instructions in super-scalar processors. IEEE Trans. Reliab. (2002)","DOI":"10.1109\/24.994913"},{"key":"18_CR26","doi-asserted-by":"crossref","unstructured":"Pattabiraman, K., et\u00a0al.: Dynamic derivation of application-specific error detectors and their implementation in hardware. In: EDCC 2006 (2006)","DOI":"10.1109\/EDCC.2006.9"},{"key":"18_CR27","unstructured":"Rela, M.Z., et\u00a0al.: Experimental evaluation of the fail-silent behaviour in programs with consistency checks. In: FTCS 1996 (1996)"},{"key":"18_CR28","doi-asserted-by":"crossref","unstructured":"Richter-Brockmann, J., et\u00a0al.: Revisiting fault adversary models - hardware faults in theory and practice. IEEE Trans. Comput. (2023)","DOI":"10.1109\/TC.2022.3164259"},{"key":"18_CR29","doi-asserted-by":"crossref","unstructured":"Rodrigues, C., et\u00a0al.: Towards a heterogeneous fault-tolerance architecture based on arm and RISC-V processors. In: IECON 2019 (2019)","DOI":"10.1109\/IECON.2019.8926844"},{"key":"18_CR30","doi-asserted-by":"crossref","unstructured":"Santos, D.A., et\u00a0al.: Characterization of a RISC-V system-on-chip under neutron radiation. In: DTIS 2021 (2021)","DOI":"10.1109\/DTIS53253.2021.9505054"},{"key":"18_CR31","unstructured":"Schuette, M.A., Shen, J.P.: Exploiting instruction-level resource parallelism for transparent, integrated control-flow monitoring. In: FTCS 1991 (1991)"},{"key":"18_CR32","doi-asserted-by":"crossref","unstructured":"Sorin, D.J.: Fault tolerant computer architecture (2009)","DOI":"10.1007\/978-3-031-01723-0"},{"key":"18_CR33","unstructured":"Tang, A., et\u00a0al.: CLKSCREW: exposing the perils of security-oblivious energy management. In: USENIX Security 2017 (2017)"},{"key":"18_CR34","doi-asserted-by":"crossref","unstructured":"Thei\u00dfing, N., et\u00a0al.: Comprehensive analysis of software countermeasures against fault attacks. In: DATE 2013 (2013)","DOI":"10.7873\/DATE.2013.092"},{"key":"18_CR35","doi-asserted-by":"crossref","unstructured":"Timmers, N., et\u00a0al.: Controlling PC on ARM using fault injection. In: FDTC 2016 (2016)","DOI":"10.1109\/FDTC.2016.18"},{"key":"18_CR36","doi-asserted-by":"crossref","unstructured":"Timmers, N., Mune, C.: Escalating privileges in linux using voltage fault injection. In: FDTC 2017 (2017)","DOI":"10.1109\/FDTC.2017.16"},{"key":"18_CR37","doi-asserted-by":"crossref","unstructured":"Upasani, G., et\u00a0al.: Framework for economical error recovery in embedded cores. In: IOLTS 2014 (2014)","DOI":"10.1109\/IOLTS.2014.6873687"},{"key":"18_CR38","doi-asserted-by":"crossref","unstructured":"Vasselle, A., et\u00a0al.: Laser-induced fault injection on smartphone bypassing the secure boot-extended version. IEEE Trans. Comput. (2020)","DOI":"10.1109\/TC.2018.2860010"},{"key":"18_CR39","unstructured":"Veripool: Verilator (nd). https:\/\/www.veripool.org\/verilator\/. Accessed 18 Apr 2024"},{"key":"18_CR40","doi-asserted-by":"crossref","unstructured":"Werner, M., et\u00a0al.: Protecting the control flow of embedded processors against fault attacks. In: CARDIS 2015 (2015)","DOI":"10.1007\/978-3-319-31271-2_10"},{"key":"18_CR41","doi-asserted-by":"crossref","unstructured":"Yuce, B., et\u00a0al.: FAME: fault-attack aware microprocessor extensions for hardware fault detection and software fault response. In: HASP 2016 (2016)","DOI":"10.1145\/2948618.2948626"}],"container-title":["Lecture Notes in Computer Science","Detection of Intrusions and Malware, and Vulnerability Assessment"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-031-97623-0_18","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,10]],"date-time":"2025-07-10T09:30:41Z","timestamp":1752139841000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-031-97623-0_18"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025]]},"ISBN":["9783031976223","9783031976230"],"references-count":41,"URL":"https:\/\/doi.org\/10.1007\/978-3-031-97623-0_18","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"value":"0302-9743","type":"print"},{"value":"1611-3349","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025]]},"assertion":[{"value":"10 July 2025","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"DIMVA","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"International Conference on Detection of Intrusions and Malware, and Vulnerability Assessment","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Graz","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Austria","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2025","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"9 July 2025","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"11 July 2025","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"22","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"dimva2025","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"https:\/\/dimva.org\/dimva2025\/","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}}]}}