{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T16:41:29Z","timestamp":1773247289760,"version":"3.50.1"},"publisher-location":"Cham","reference-count":17,"publisher":"Springer Nature Switzerland","isbn-type":[{"value":"9783031998539","type":"print"},{"value":"9783031998546","type":"electronic"}],"license":[{"start":{"date-parts":[[2025,8,27]],"date-time":"2025-08-27T00:00:00Z","timestamp":1756252800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2025,8,27]],"date-time":"2025-08-27T00:00:00Z","timestamp":1756252800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2026]]},"DOI":"10.1007\/978-3-031-99854-6_2","type":"book-chapter","created":{"date-parts":[[2025,8,26]],"date-time":"2025-08-26T05:09:40Z","timestamp":1756184980000},"page":"24-37","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":4,"title":["Scalable Code Generation for\u00a0RTL Simulation of\u00a0Deep Learning Accelerators With MLIR"],"prefix":"10.1007","author":[{"given":"Jie","family":"Tong","sequence":"first","affiliation":[]},{"given":"Wan-Luan","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Umit","family":"Yusuf Ogras","sequence":"additional","affiliation":[]},{"given":"Tsung-Wei","family":"Huang","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2025,8,27]]},"reference":[{"key":"2_CR1","doi-asserted-by":"crossref","unstructured":"Beamer, S., Donofrio, D.: Efficiently exploiting low activity factors to accelerate RTL simulation. In: 2020 57th ACM\/IEEE DAC, pp.\u00a01\u20136. IEEE (2020)","DOI":"10.1109\/DAC18072.2020.9218632"},{"key":"2_CR2","doi-asserted-by":"crossref","unstructured":"Genc, H., et\u00a0al.: Gemmini: enabling systematic deep-learning architecture evaluation via full-stack integration. In: DAC 2021, pp. 769\u2013774. IEEE (2021)","DOI":"10.1109\/DAC18074.2021.9586216"},{"key":"2_CR3","doi-asserted-by":"crossref","unstructured":"Huang, T.W., Lin, D.L., Lin, C.X., Lin, Y.: TaskFlow: a lightweight parallel and heterogeneous task graph computing system. IEEE Trans. Parallel Distr. Syst. 33(6) (TPDS) (2022)","DOI":"10.1109\/TPDS.2021.3104255"},{"key":"2_CR4","doi-asserted-by":"crossref","unstructured":"Huang, T.W., Wong, M.: OpenTimer: a high-performance timing analysis tool. In: IEEE\/ACM International Conference on Computer-Aided Design (ICCAD) (2015)","DOI":"10.1109\/ICCAD.2015.7372666"},{"key":"2_CR5","doi-asserted-by":"crossref","unstructured":"Izraelevitz, A., et\u00a0al.: Reusability is FIRRTL ground: hardware construction languages, compiler frameworks, and transformations. In: 2017 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), pp. 209\u2013216. IEEE (2017)","DOI":"10.1109\/ICCAD.2017.8203780"},{"key":"2_CR6","doi-asserted-by":"crossref","unstructured":"Jia, L., Luo, Z., Lu, L., Liang, Y.: TensorLib: a spatial accelerator generation framework for tensor algebra. In: 2021 58th ACM\/IEEE Design Automation Conference (DAC), pp. 865\u2013870. IEEE (2021)","DOI":"10.1109\/DAC18074.2021.9586329"},{"key":"2_CR7","doi-asserted-by":"crossref","unstructured":"Lattner, C., et al.: MLIR: scaling compiler infrastructure for domain specific computation. In: CGO 2021, pp. 2\u201314. IEEE (2021)","DOI":"10.1109\/CGO51591.2021.9370308"},{"key":"2_CR8","doi-asserted-by":"crossref","unstructured":"Lin, D.L., Huang, T.W.: Efficient GPU computation using task graph parallelism. In: European Conference on Parallel and Distributed Computing (Euro-Par) (2021)","DOI":"10.1007\/978-3-030-85665-6_27"},{"key":"2_CR9","doi-asserted-by":"crossref","unstructured":"Lin, D.L., Huang, T.W., Miguel, J.S., Ogras, U.: TaroRTL: accelerating RTL simulation using coroutine-based heterogeneous task graph scheduling. In: Euro-Par 2024 (2024)","DOI":"10.1007\/978-3-031-69583-4_11"},{"key":"2_CR10","doi-asserted-by":"crossref","unstructured":"Lin, D.L., Ren, H., Zhang, Y., Khailany, B., Huang, T.W.: From RTL to CUDA: a GPU acceleration flow for RTL simulation with batch stimulus. In: ACM International Conference on Parallel Processing (ICPP) (2022)","DOI":"10.1145\/3545008.3545091"},{"key":"2_CR11","doi-asserted-by":"crossref","unstructured":"Qin, E., et al.: SIGMA: a sparse and irregular GEMM accelerator with flexible interconnects for DNN training. In: 2020 IEEE International Symposium on High Performance Computer Architecture (HPCA), pp. 58\u201370. IEEE (2020)","DOI":"10.1109\/HPCA47549.2020.00015"},{"key":"2_CR12","unstructured":"Snyder, W.: Verilator: open simulation goes multithreaded. In: ORConf (2018)"},{"key":"2_CR13","doi-asserted-by":"crossref","unstructured":"Tong, J., Chang, L., Ogras, U.Y., Huang, T.W.: BatchSim: parallel RTL simulation using inter-cycle batching and task graph parallelism. In: 2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 789\u2013793. IEEE (2024)","DOI":"10.1109\/ISVLSI61997.2024.00155"},{"key":"2_CR14","doi-asserted-by":"crossref","unstructured":"Trevisan\u00a0Jost, T., Thangamani, A., Colin, R., Loechner, V., Genaud, S., Bramas, B.: GPU code generation of cardiac electrophysiology simulation with MLIR. In: European Conference on Parallel Processing, pp. 549\u2013563. Springer (2023)","DOI":"10.1007\/978-3-031-39698-4_37"},{"key":"2_CR15","doi-asserted-by":"crossref","unstructured":"Wang, H., Beamer, S.: RepCut: superlinear parallel RTL simulation with replication-aided partitioning. In: Proceedings of the 28th ACM International Conference on ASPLOS, vol. 3, pp. 572\u2013585 (2023)","DOI":"10.1145\/3582016.3582034"},{"key":"2_CR16","doi-asserted-by":"crossref","unstructured":"Wang, H., Nijssen, T., Beamer, S.: Don\u2019t repeat yourself! coarse-grained circuit deduplication to accelerate RTL simulation. In: Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, vol. 4, pp. 79\u201393 (2024)","DOI":"10.1145\/3622781.3674184"},{"key":"2_CR17","doi-asserted-by":"crossref","unstructured":"Zhou, K., Liang, Y., Lin, Y., Wang, R., Huang, R.: Khronos: fusing memory access for improved hardware RTL simulation. In: Proceedings of the 56th Annual IEEE\/ACM International Symposium on Microarchitecture, pp. 180\u2013193 (2023)","DOI":"10.1145\/3613424.3614301"}],"container-title":["Lecture Notes in Computer Science","Euro-Par 2025: Parallel Processing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-031-99854-6_2","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,9,3]],"date-time":"2025-09-03T09:43:59Z","timestamp":1756892639000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-031-99854-6_2"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,8,27]]},"ISBN":["9783031998539","9783031998546"],"references-count":17,"URL":"https:\/\/doi.org\/10.1007\/978-3-031-99854-6_2","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"value":"0302-9743","type":"print"},{"value":"1611-3349","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,8,27]]},"assertion":[{"value":"27 August 2025","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"The authors have no competing interests to declare that are relevant to the content of this article.","order":1,"name":"Ethics","group":{"name":"EthicsHeading","label":"Disclosure of Interests"}},{"value":"Euro-Par","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"European Conference on Parallel Processing","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Dresden","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Germany","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2025","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"25 August 2025","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"29 August 2025","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"31","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"europar2025","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"https:\/\/2025.euro-par.org\/","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}}]}}