{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,11]],"date-time":"2025-09-11T20:27:39Z","timestamp":1757622459840,"version":"3.44.0"},"publisher-location":"Cham","reference-count":60,"publisher":"Springer Nature Switzerland","isbn-type":[{"type":"print","value":"9783032006264"},{"type":"electronic","value":"9783032006271"}],"license":[{"start":{"date-parts":[[2025,1,1]],"date-time":"2025-01-01T00:00:00Z","timestamp":1735689600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2025,1,1]],"date-time":"2025-01-01T00:00:00Z","timestamp":1735689600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025]]},"DOI":"10.1007\/978-3-032-00627-1_6","type":"book-chapter","created":{"date-parts":[[2025,8,9]],"date-time":"2025-08-09T04:21:59Z","timestamp":1754713319000},"page":"106-126","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Fast and Efficient Secure L1 Caches for SMT"],"prefix":"10.1007","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-7133-1515","authenticated-orcid":false,"given":"Lukas","family":"Giner","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0009-0000-9230-0833","authenticated-orcid":false,"given":"Roland","family":"Czerny","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0009-0005-8968-879X","authenticated-orcid":false,"given":"Simon","family":"Lammer","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0009-0008-5841-4077","authenticated-orcid":false,"given":"Aaron","family":"Giner","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0009-0004-5794-3832","authenticated-orcid":false,"given":"Paul","family":"Gollob","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0009-0002-0569-1704","authenticated-orcid":false,"given":"Jonas","family":"Juffinger","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7977-3246","authenticated-orcid":false,"given":"Daniel","family":"Gruss","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2025,8,10]]},"reference":[{"key":"6_CR1","unstructured":"Al-Tarawneh, M.: An investigation of the impact of instruction cache (i-cache) organization on power-performance trade-offs in the design of scalar processors. Eur. J. Sci. Res. 115, 7\u201326 (2013)"},{"key":"6_CR2","doi-asserted-by":"crossref","unstructured":"Ar\u0131kan, K., et al.: TEE-SHirT: scalable leakage-free cache hierarchies for TEEs. In: NDSS (2024)","DOI":"10.14722\/ndss.2024.24390"},{"key":"6_CR3","unstructured":"Beckmann, N., Sanchez, D.: Jigsaw: scalable software-defined caches. In: PACT (2013)"},{"key":"6_CR4","unstructured":"Bernstein, D.J.: Cache-Timing Attacks on AES (2005). http:\/\/cr.yp.to\/antiforgery\/cachetiming-20050414.pdf"},{"key":"6_CR5","doi-asserted-by":"crossref","unstructured":"Binkert, N., et al.: The gem5 simulator. ACM SIGARCH Comput. Archit. News (2011)","DOI":"10.1145\/2024716.2024718"},{"key":"6_CR6","doi-asserted-by":"crossref","unstructured":"Bourgeat, T., Lebedev, I., Wright, A., Zhang, S., Devadas, S.: MI6: secure enclaves in a speculative out-of-order processor. In: MICRO (2019)","DOI":"10.1145\/3352460.3358310"},{"key":"6_CR7","unstructured":"Brasser, F., M\u00fcller, U., Dmitrienko, A., Kostiainen, K., Capkun, S., Sadeghi, A.R.: Software grand exposure: SGX cache attacks are practical. In: WOOT (2017)"},{"key":"6_CR8","doi-asserted-by":"crossref","unstructured":"Canella, C., et al.: Fallout: leaking data on meltdown-resistant CPUs. In: CCS (2019)","DOI":"10.1145\/3319535.3363219"},{"key":"6_CR9","unstructured":"Dessouky, G., Frassetto, T., Sadeghi, A.R.: HybCache: hybrid side-channel-resilient caches for trusted execution environments. In: USENIX Security (2019)"},{"key":"6_CR10","doi-asserted-by":"crossref","unstructured":"Dessouky, G., Gruler, A., Mahmoody, P., Sadeghi, A.R., Stapf, E.: Chunked-cache: on-demand and scalable cache isolation for security architectures. In: NDSS (2022)","DOI":"10.14722\/ndss.2022.23110"},{"key":"6_CR11","doi-asserted-by":"crossref","unstructured":"Domnitser, L., Jaleel, A., Loew, J., Abu-Ghazaleh, N., Ponomarev, D.: Non-monopolizable caches: low-complexity mitigation of cache side channel attacks. ACM TACO 8(4) (2011)","DOI":"10.1145\/2086696.2086714"},{"key":"6_CR12","unstructured":"Frumusanu, A.: Apple Announces The Apple Silicon M1: Ditching x86 - What to Expect, Based on A14 (2020). https:\/\/www.anandtech.com\/show\/16226\/apple-silicon-m1-a14-deep-dive"},{"key":"6_CR13","doi-asserted-by":"crossref","unstructured":"Ge, Q., Yarom, Y., Chothia, T., Heiser, G.: Time protection: the missing OS abstraction. In: EuroSys (2019)","DOI":"10.1145\/3302424.3303976"},{"key":"6_CR14","doi-asserted-by":"crossref","unstructured":"Giner, L., et al.: Scatter and split securely: defeating cache contention and occupancy attacks. In: USENIX Security (2023)","DOI":"10.1109\/SP46215.2023.10179440"},{"key":"6_CR15","unstructured":"Giner, L.: CacheSim Cache Simulator (2023). https:\/\/github.com\/isec-tugraz\/CacheSim"},{"key":"6_CR16","doi-asserted-by":"crossref","unstructured":"G\u00f6tzfried, J., Eckert, M., Schinzel, S., M\u00fcller, T.: Cache attacks on intel SGX. In: EuroSec (2017)","DOI":"10.1145\/3065913.3065915"},{"key":"6_CR17","unstructured":"Gruss, D., Spreitzer, R., Mangard, S.: Cache template attacks: automating attacks on inclusive last-level caches. In: USENIX Security (2015)"},{"key":"6_CR18","doi-asserted-by":"crossref","unstructured":"Herdrich, A., et al.: Cache QoS: from concept to reality in the Intel Xeon processor E5-2600 v3 product family. In: HPCA (2016)","DOI":"10.1109\/HPCA.2016.7446102"},{"key":"6_CR19","doi-asserted-by":"crossref","unstructured":"Huang, D., Ye, D., He, Q., Chen, J., Ye, K.: Virt-LM: a benchmark for live migration of virtual machine. In: ACM\/SPEC ICPE (2011)","DOI":"10.1145\/1958746.1958790"},{"key":"6_CR20","unstructured":"Intel: Improving Real-Time Performance by Utilizing Cache Allocation Technology: Enhancing Performance via Allocation of the Processor\u2019s Cache (2015). https:\/\/www.intel.com\/content\/dam\/www\/public\/us\/en\/documents\/white-papers\/cache-allocation-technology-white-paper.pdf"},{"key":"6_CR21","unstructured":"Intel: Intel Software Guard Extensions (Intel SGX) (2024). https:\/\/www.intel.com\/content\/www\/us\/en\/products\/docs\/accelerator-engines\/software-guard-extensions.html"},{"key":"6_CR22","doi-asserted-by":"crossref","unstructured":"Jiang, Z.H., Fei, Y.: A novel cache bank timing attack. In: ICCAD (2017)","DOI":"10.1109\/ICCAD.2017.8203771"},{"key":"6_CR23","doi-asserted-by":"crossref","unstructured":"Kiriansky, V., Lebedev, I., Amarasinghe, S., Devadas, S., Emer, J.: DAWG: a defense against cache timing attacks in speculative execution processors. In: MICRO (2018)","DOI":"10.1109\/MICRO.2018.00083"},{"key":"6_CR24","doi-asserted-by":"crossref","unstructured":"Kong, J., Ac\u0131i\u00e7mez, O., Seifert, J.P., Zhou, H.: Deconstructing new cache designs for thwarting software cache-based side channel attacks. In: CSAW, p.\u00a025 (2008)","DOI":"10.1145\/1456508.1456514"},{"key":"6_CR25","unstructured":"Larabel, M.: An Early Look At The L1 Terminal Fault \u201cL1TF\u201d Performance Impact on Virtual Machines (2018). https:\/\/www.phoronix.com\/review\/l1tf-early-look"},{"key":"6_CR26","doi-asserted-by":"crossref","unstructured":"Li, S., Chen, K., Ahn, J.H., Brockman, J.B., Jouppi, N.P.: CACTI-P: architecture-level modeling for SRAM-based structures with advanced leakage reduction techniques. In: ICCAD (2011)","DOI":"10.1109\/ICCAD.2011.6105405"},{"key":"6_CR27","unstructured":"Lipp, M., Gruss, D., Spreitzer, R., Maurice, C., Mangard, S.: ARMageddon: cache attacks on mobile devices. In: USENIX Security (2016)"},{"key":"6_CR28","unstructured":"Lipp, M., et al.: Meltdown: reading kernel memory from user space. In: USENIX Security (2018)"},{"key":"6_CR29","doi-asserted-by":"crossref","unstructured":"Lipp, M., et al.: Meltdown: reading kernel memory from user space. Commun. ACM 63(6) (2020)","DOI":"10.1145\/3357033"},{"key":"6_CR30","doi-asserted-by":"crossref","unstructured":"Liu, F., et al.: Catalyst: defeating last-level cache side channel attacks in cloud computing. In: HPCA (2016)","DOI":"10.1109\/HPCA.2016.7446082"},{"issue":"5","key":"6_CR31","doi-asserted-by":"publisher","first-page":"8","DOI":"10.1109\/MM.2016.85","volume":"36","author":"F Liu","year":"2016","unstructured":"Liu, F., Wu, H., Mai, K., Lee, R.B.: Newcache: secure cache architecture thwarting cache side-channel attacks. IEEE Micro 36(5), 8\u201316 (2016)","journal-title":"IEEE Micro"},{"key":"6_CR32","doi-asserted-by":"crossref","unstructured":"Liu, F., Yarom, Y., Ge, Q., Heiser, G., Lee, R.B.: Last-level cache side-channel attacks are practical. In: S &P (2015)","DOI":"10.1109\/SP.2015.43"},{"key":"6_CR33","unstructured":"Lowe-Power, J., et al.: The gem5 simulator: version 20.0+ (2020)"},{"key":"6_CR34","unstructured":"Mandelblat, J.: Technology Insight: Intel\u2019s Next Generation Microarchitecture Code Name Skylake (2015). https:\/\/en.wikichip.org\/w\/images\/8\/8f\/Technology_Insight_Intel%E2%80%99s_Next_Generation_Microarchitecture_Code_Name_Skylake.pdf"},{"key":"6_CR35","doi-asserted-by":"crossref","unstructured":"Moghimi, A., Irazoqui, G., Eisenbarth, T.: CacheZoom: how SGX amplifies the power of cache attacks. In: CHES (2017)","DOI":"10.1007\/978-3-319-66787-4_4"},{"key":"6_CR36","doi-asserted-by":"crossref","unstructured":"Mohammad, B.: Embedded Memory Design for Multi-Core and Systems on Chip, Analog Circuits and Signal Processing, vol.\u00a0116. Springer (2014)","DOI":"10.1007\/978-1-4614-8881-1"},{"key":"6_CR37","doi-asserted-by":"crossref","unstructured":"Muralimanohar, N., Balasubramonian, R., Jouppi, N.P.: CACTI 6.0: a tool to model large caches. HP Lab. 27, 28 (2009)","DOI":"10.1109\/MM.2008.2"},{"key":"6_CR38","doi-asserted-by":"crossref","unstructured":"Nagarajan, V., Sorin, D.J., Hill, M.D., Wood, D.A.: A primer on memory consistency and cache coherence. Springer Nature (2020)","DOI":"10.1007\/978-3-031-01764-3"},{"key":"6_CR39","doi-asserted-by":"crossref","unstructured":"Osvik, D.A., Shamir, A., Tromer, E.: Cache attacks and countermeasures: the case of AES. In: CT-RSA (2006)","DOI":"10.1007\/11605805_1"},{"key":"6_CR40","doi-asserted-by":"crossref","unstructured":"Qureshi, M.K.: CEASER: mitigating conflict-based cache attacks via encrypted-address and remapping. In: MICRO (2018)","DOI":"10.1109\/MICRO.2018.00068"},{"key":"6_CR41","doi-asserted-by":"crossref","unstructured":"Qureshi, M.K.: New attacks and defense for encrypted-address cache. In: ISCA (2019)","DOI":"10.1145\/3307650.3322246"},{"key":"6_CR42","doi-asserted-by":"crossref","unstructured":"Saileshwar, G., Kariyappa, S., Qureshi, M.: Bespoke cache enclaves: fine-grained and scalable isolation from cache side-channels via flexible set-partitioning. In: SEED (2021)","DOI":"10.1109\/SEED51797.2021.00015"},{"key":"6_CR43","unstructured":"Saileshwar, G., Qureshi, M.K.: MIRAGE: mitigating conflict-based cache attacks with a practical fully-associative design. In: USENIX Security (2021)"},{"key":"6_CR44","doi-asserted-by":"crossref","unstructured":"Sanchez, D., Kozyrakis, C.: Vantage: scalable and efficient fine-grain cache partitioning. In: ISCA (2011)","DOI":"10.1145\/2000064.2000073"},{"key":"6_CR45","doi-asserted-by":"crossref","unstructured":"van Schaik, S., et al.: RIDL: rogue in-flight data load. In: S &P (2019)","DOI":"10.1109\/SP.2019.00087"},{"key":"6_CR46","doi-asserted-by":"crossref","unstructured":"van Schaik, S., Minkin, M., Kwong, A., Genkin, D., Yarom, Y.: CacheOut: leaking data on intel CPUs via cache evictions. In: S &P (2021)","DOI":"10.1109\/SP40001.2021.00064"},{"key":"6_CR47","doi-asserted-by":"crossref","unstructured":"Schwarz, M., et al.: ZombieLoad: cross-privilege-boundary data sampling. In: CCS (2019)","DOI":"10.1145\/3319535.3354252"},{"key":"6_CR48","doi-asserted-by":"crossref","unstructured":"Schwarz, M., Weiser, S., Gruss, D., Maurice, C., Mangard, S.: Malware guard extension: using SGX to conceal cache attacks. In: DIMVA (2017)","DOI":"10.1007\/978-3-319-60876-1_1"},{"key":"6_CR49","doi-asserted-by":"crossref","unstructured":"Schwarzl, M., Schuster, T., Schwarz, M., Gruss, D.: Speculative dereferencing of registers: reviving foreshadow. In: FC (2021)","DOI":"10.1007\/978-3-662-64322-8_15"},{"key":"6_CR50","doi-asserted-by":"crossref","unstructured":"Schwedock, B.C., Beckmann, N.: Jumanji: the case for dynamic NUCA in the datacenter. In: MICRO (2020)","DOI":"10.1109\/MICRO50266.2020.00061"},{"key":"6_CR51","doi-asserted-by":"crossref","unstructured":"Tan, Q., Zeng, Z., Bu, K., Ren, K.: PhantomCache: obfuscating cache conflicts with localized randomization. In: NDSS (2020)","DOI":"10.14722\/ndss.2020.24086"},{"key":"6_CR52","unstructured":"Townley, D., Ar\u0131kan, K., Liu, Y.D., Ponomarev, D., Ergin, O.: Composable cachelets: protecting enclaves from cache $$\\{$$side-channel$$\\}$$ attacks. In: USENIX Security, pp. 2839\u20132856 (2022)"},{"key":"6_CR53","doi-asserted-by":"crossref","unstructured":"Unterluggauer, T., Harris, A., Constable, S., Liu, F., Rozas, C.: Chameleon cache: approximating fully associative caches with random replacement to prevent contention-based cache attacks. In: SEED (2022)","DOI":"10.1109\/SEED55351.2022.00009"},{"key":"6_CR54","unstructured":"Van\u00a0Bulck, J., et al.: Foreshadow: extracting the keys to the intel SGX kingdom with transient out-of-order execution. In: USENIX Security (2018)"},{"issue":"2","key":"6_CR55","doi-asserted-by":"publisher","first-page":"494","DOI":"10.1145\/1273440.1250723","volume":"35","author":"Z Wang","year":"2007","unstructured":"Wang, Z., Lee, R.B.: New cache designs for thwarting software cache-based side channel attacks. ACM SIGARCH Comput. Archit. News 35(2), 494 (2007)","journal-title":"ACM SIGARCH Comput. Archit. News"},{"key":"6_CR56","unstructured":"Weisse, O., et al.: Foreshadow-NG: Breaking the Virtual Memory Abstraction with Transient Out-of-Order Execution (2018). https:\/\/foreshadowattack.eu\/"},{"key":"6_CR57","unstructured":"Werner, M., Unterluggauer, T., Giner, L., Schwarz, M., Gruss, D., Mangard, S.: ScatterCache: thwarting cache attacks via cache set randomization. In: USENIX Security (2019)"},{"issue":"1","key":"6_CR58","first-page":"14","volume":"16","author":"H Wu","year":"2017","unstructured":"Wu, H., Liu, F., Lee, R.B.: Cloud server benchmark suite for evaluating new hardware architectures. IEEE CAL 16(1), 14\u201317 (2017)","journal-title":"IEEE CAL"},{"key":"6_CR59","doi-asserted-by":"crossref","unstructured":"Yan, M., Sprabery, R., Gopireddy, B., Fletcher, C., Campbell, R., Torrellas, J.: Attack directories, not caches: side channel attacks in a non-inclusive world. In: S &P (2019)","DOI":"10.1109\/SP.2019.00004"},{"key":"6_CR60","unstructured":"Yarom, Y., Falkner, K.: Flush+reload: a high resolution, low noise, L3 cache side-channel attack. In: USENIX Security (2014)"}],"container-title":["Lecture Notes in Computer Science","Availability, Reliability and Security"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-032-00627-1_6","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,9,8]],"date-time":"2025-09-08T20:05:04Z","timestamp":1757361904000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-032-00627-1_6"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025]]},"ISBN":["9783032006264","9783032006271"],"references-count":60,"URL":"https:\/\/doi.org\/10.1007\/978-3-032-00627-1_6","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2025]]},"assertion":[{"value":"10 August 2025","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"ARES","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"International Conference on Availability, Reliability and Security","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Ghent","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Belgium","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2025","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"11 August 2025","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"14 August 2025","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"20","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"ares-12025","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"https:\/\/2025.ares-conference.eu","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}}]}}