{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,2]],"date-time":"2025-10-02T00:38:58Z","timestamp":1759365538718,"version":"build-2065373602"},"publisher-location":"Cham","reference-count":52,"publisher":"Springer Nature Switzerland","isbn-type":[{"value":"9783032067531","type":"print"},{"value":"9783032067548","type":"electronic"}],"license":[{"start":{"date-parts":[[2025,10,2]],"date-time":"2025-10-02T00:00:00Z","timestamp":1759363200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2025,10,2]],"date-time":"2025-10-02T00:00:00Z","timestamp":1759363200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2026]]},"DOI":"10.1007\/978-3-032-06754-8_17","type":"book-chapter","created":{"date-parts":[[2025,10,1]],"date-time":"2025-10-01T08:23:08Z","timestamp":1759306988000},"page":"450-487","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Runtime Code Generation for\u00a0Constant-Time Secret-Indexed Array Accesses: Applications to\u00a0PERK and\u00a0NTRU"],"prefix":"10.1007","author":[{"given":"D\u00e9cio Luiz","family":"Gazzoni Filho","sequence":"first","affiliation":[]},{"given":"Rafael G.","family":"Flores e Silva","sequence":"additional","affiliation":[]},{"given":"Alessandro","family":"Budroni","sequence":"additional","affiliation":[]},{"given":"Marco","family":"Palumbi","sequence":"additional","affiliation":[]},{"given":"Gora","family":"Adj","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2025,10,2]]},"reference":[{"key":"17_CR1","unstructured":"Aaraj, N., et al.: PERK. Technical report, National Institute of Standards and Technology (2024). available at https:\/\/csrc.nist.gov\/Projects\/pqc-dig-sig\/round-2-additional-signatures"},{"key":"17_CR2","doi-asserted-by":"publisher","unstructured":"Abdulrahman, A., Chen, J.P., Chen, Y.J., Hwang, V., Kannwischer, M.J., Yang, B.Y.: Multi-moduli NTTs for saber on Cortex-M3 and Cortex-M4. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2022(1), 127\u2013151 (2022). https:\/\/doi.org\/10.46586\/tches.v2022.i1.127-151","DOI":"10.46586\/tches.v2022.i1.127-151"},{"key":"17_CR3","doi-asserted-by":"publisher","unstructured":"Abdulrahman, A., Hwang, V., Kannwischer, M.J., Sprenkels, A.: Faster kyber and dilithium on the Cortex-M4. In: Ateniese, G., Venturi, D. (eds.) ACNS 22: 20th International Conference on Applied Cryptography and Network Security. LNCS, vol. 13269, pp. 853\u2013871. Springer, Cham (2022). https:\/\/doi.org\/10.1007\/978-3-031-09234-3_42","DOI":"10.1007\/978-3-031-09234-3_42"},{"key":"17_CR4","doi-asserted-by":"publisher","unstructured":"Adomnicai, A., Peyrin, T.: Fixslicing AES-like ciphers. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2021(1), 402\u2013425 (2021). https:\/\/doi.org\/10.46586\/tches.v2021.i1.402-425, https:\/\/tches.iacr.org\/index.php\/TCHES\/article\/view\/8739","DOI":"10.46586\/tches.v2021.i1.402-425"},{"key":"17_CR5","unstructured":"Advanced Encryption Standard (AES). National Institute of Standards and Technology, NIST FIPS PUB 197, U.S. Department of Commerce (2001)"},{"key":"17_CR6","unstructured":"Albrecht, M.R., et al.: Classic McEliece. Technical report, National Institute of Standards and Technology (2022). available at https:\/\/csrc.nist.gov\/projects\/post-quantum-cryptography\/round-4-submissions"},{"key":"17_CR7","doi-asserted-by":"publisher","unstructured":"Alkim, E., et al.: Polynomial multiplication in NTRU prime. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2021(1), 217\u2013238 (2021). https:\/\/doi.org\/10.46586\/tches.v2021.i1.217-238, https:\/\/tches.iacr.org\/index.php\/TCHES\/article\/view\/8733","DOI":"10.46586\/tches.v2021.i1.217-238"},{"key":"17_CR8","doi-asserted-by":"publisher","unstructured":"Anastasova, M., Azarderakhsh, R., Kermani, M.M., Beshaj, L.: Time-efficient finite field microarchitecture design for Curve448 and Ed448 on cortex-M4. In: Seo, S.H., Seo, H. (eds.) ICISC 22: 25th International Conference on Information Security and Cryptology. LNCS, vol. 13849, pp. 292\u2013314. Springer, Cham (2022). https:\/\/doi.org\/10.1007\/978-3-031-29371-9_15","DOI":"10.1007\/978-3-031-29371-9_15"},{"key":"17_CR9","doi-asserted-by":"crossref","unstructured":"Anastasova, M., Bisheh-Niasar, M., Azarderakhsh, R., Kermani, M.M.: Compressed SIKE round 3 on ARM Cortex-M4. Cryptology ePrint Archive, Report 2021\/1511 (2021). https:\/\/eprint.iacr.org\/2021\/1511","DOI":"10.1007\/978-3-030-90022-9_24"},{"key":"17_CR10","unstructured":"Arm Limited: Arm Cortex-M4 datasheet (2020). https:\/\/developer.arm.com\/documentation\/102832\/latest\/"},{"key":"17_CR11","unstructured":"Arm Limited: Arm\u00ae Cortex\u00ae\u00a0-M4 processor technical reference manual revision r0p1 (2020). https:\/\/developer.arm.com\/documentation\/100166\/0001\/"},{"key":"17_CR12","unstructured":"Arm Limited: Arm\u00ae\u00a0v7-M architecture reference manual (2021). https:\/\/developer.arm.com\/documentation\/ddi0403\/ee\/"},{"key":"17_CR13","unstructured":"Arm Limited: Arm CPU security update: Timing side channel attacks on TrustZone enabled Cortex-M based systems (2025). https:\/\/developer.arm.com\/documentation\/110390\/1-1\/"},{"key":"17_CR14","unstructured":"Baldi, M., et al.: LESS \u2014 Linear Equivalence Signature Scheme. Technical report, National Institute of Standards and Technology (2024). available at https:\/\/csrc.nist.gov\/Projects\/pqc-dig-sig\/round-2-additional-signatures"},{"key":"17_CR15","doi-asserted-by":"publisher","unstructured":"Becker, H., Hwang, V., Kannwischer, M.J., Panny, L., Yang, B.Y.: Efficient multiplication of somewhat small integers using number-theoretic transforms. In: Cheng, C.M., Akiyama, M. (eds.) IWSEC 22: 17th International Workshop on Security, Advances in Information and Computer Security. LNCS, vol. 13504, pp. 3\u201323. Springer, Cham (2022). https:\/\/doi.org\/10.1007\/978-3-031-15255-9_1","DOI":"10.1007\/978-3-031-15255-9_1"},{"key":"17_CR16","unstructured":"Bernstein, D.J.: Cache-timing attacks on AES (2005). https:\/\/cr.yp.to\/antiforgery\/cachetiming-20050414.pdf"},{"key":"17_CR17","unstructured":"Bernstein, D.J.: Djbsort software library (2019). https:\/\/sorting.cr.yp.to\/"},{"key":"17_CR18","doi-asserted-by":"publisher","unstructured":"Bernstein, D.J., Chuengsatiansup, C., Lange, T., van Vredendaal, C.: NTRU prime: reducing attack surface at low cost. In: Adams, C., Camenisch, J. (eds.) SAC 2017: 24th Annual International Workshop on Selected Areas in Cryptography. LNCS, vol. 10719, pp. 235\u2013260. Springer, Cham (2017). https:\/\/doi.org\/10.1007\/978-3-319-72565-9_12","DOI":"10.1007\/978-3-319-72565-9_12"},{"key":"17_CR19","doi-asserted-by":"publisher","unstructured":"Bettaieb, S., Bidoux, L., Budroni, A., Palumbi, M., Perin, L.P.: Enabling PERK and other MPC-in-the-head signatures on resource-constrained devices. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2024(4), 84\u2013109 (2024). https:\/\/doi.org\/10.46586\/tches.v2024.i4.84-109","DOI":"10.46586\/tches.v2024.i4.84-109"},{"key":"17_CR20","doi-asserted-by":"publisher","unstructured":"Biham, E.: A fast new DES implementation in software. In: Biham, E. (eds.) Fast Software Encryption. FSE 1997. LNCS, vol.\u00a01267, pp. 260\u2013272. Springer, Berlin, Heidelberg (1997). https:\/\/doi.org\/10.1007\/BFb0052352","DOI":"10.1007\/BFb0052352"},{"key":"17_CR21","unstructured":"Budroni, A., Canales-Mart\u00ednez, I.A., Perin, L.P.: SoK: methods for sampling random permutations in post-quantum cryptography. Cryptology ePrint Archive, Report 2024\/008 (2024). https:\/\/eprint.iacr.org\/2024\/008"},{"key":"17_CR22","unstructured":"Chen, C., et al.: NTRU. Technical report, National Institute of Standards and Technology (2020). available at https:\/\/csrc.nist.gov\/projects\/post-quantum-cryptography\/post-quantum-cryptography-standardization\/round-3-submissions"},{"key":"17_CR23","doi-asserted-by":"publisher","unstructured":"Chen, M.S., Chou, T.: Classic McEliece on the ARM Cortex-M4. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2021(3), 125\u2013148 (2021). https:\/\/doi.org\/10.46586\/tches.v2021.i3.125-148, https:\/\/tches.iacr.org\/index.php\/TCHES\/article\/view\/8970","DOI":"10.46586\/tches.v2021.i3.125-148"},{"key":"17_CR24","doi-asserted-by":"publisher","unstructured":"Chung, C.M.M., Hwang, V., Kannwischer, M.J., Seiler, G., Shih, C.J., Yang, B.Y.: NTT multiplication for NTT-unfriendly rings. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2021(2), 159\u2013188 (2021). https:\/\/doi.org\/10.46586\/tches.v2021.i2.159-188, https:\/\/tches.iacr.org\/index.php\/TCHES\/article\/view\/8791","DOI":"10.46586\/tches.v2021.i2.159-188"},{"key":"17_CR25","doi-asserted-by":"publisher","unstructured":"Dhem, J.F., Koeune, F., Leroux, P.A., Mestr\u00e9, P., Quisquater, J.J., Willems, J.L.: A practical implementation of the timing attack. In: Quisquater, J.J., Schneier, B. (eds.) Smart Card Research and Applications. CARDIS 1998. LNCS, vol. 1820, pp. 167\u2013182. Springer, Berlin, Heidelberg (2000). https:\/\/doi.org\/10.1007\/10721064_15","DOI":"10.1007\/10721064_15"},{"key":"17_CR26","doi-asserted-by":"publisher","unstructured":"Durstenfeld, R.: Algorithm 235: random permutation. Commun. ACM 7(7), 420 (1964). https:\/\/doi.org\/10.1145\/364520.364540","DOI":"10.1145\/364520.364540"},{"key":"17_CR27","doi-asserted-by":"publisher","unstructured":"Filho, D.L.G., Silva, T.S.R., L\u00f3pez-Hern\u00e1ndez, J.C.: Efficient isochronous fixed-weight sampling with applications to NTRU. IACR Commun. Cryptol. (CiC) 1(2), 14 (2024). https:\/\/doi.org\/10.62056\/a6n59qgxq","DOI":"10.62056\/a6n59qgxq"},{"key":"17_CR28","unstructured":"Fisher, R.A., Yates, F.: Statistical Tables for Biological, 6th edn. Agricultural and Medical Research. Oliver & Boyd, London (1938)"},{"key":"17_CR29","doi-asserted-by":"publisher","unstructured":"Hamburg, M.: Accelerating AES with vector permute instructions. In: Clavier, C., Gaj, K. (eds.) Cryptographic Hardware and Embedded Systems \u2013 CHES\u00a02009. LNCS, vol.\u00a05747, pp. 18\u201332. Springer, Berlin, Heidelberg (2009). https:\/\/doi.org\/10.1007\/978-3-642-04138-9_2","DOI":"10.1007\/978-3-642-04138-9_2"},{"key":"17_CR30","doi-asserted-by":"publisher","unstructured":"Huang, J., Zhang, J., Zhao, H., Liu, Z., Cheung, R.C.C., Ko\u00e7, \u00c7.K., Chen, D.: Improved plantard arithmetic for lattice-based cryptography. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2022(4), 614\u2013636 (2022). https:\/\/doi.org\/10.46586\/tches.v2022.i4.614-636","DOI":"10.46586\/tches.v2022.i4.614-636"},{"key":"17_CR31","unstructured":"Kannwischer, M.J., Krausz, M., Petri, R., Yang, S.Y.: PQM4: benchmarking NIST additional post-quantum signature schemes on microcontrollers. Cryptology ePrint Archive, Report 2024\/112 (2024). https:\/\/eprint.iacr.org\/2024\/112"},{"key":"17_CR32","unstructured":"Kannwischer, M.J., Rijneveld, J., Schwabe, P., Stoffelen, K.: PQM4: testing and benchmarking NIST PQC on ARM Cortex-M4. Cryptology ePrint Archive, Report 2019\/844 (2019). https:\/\/eprint.iacr.org\/2019\/844"},{"key":"17_CR33","doi-asserted-by":"publisher","unstructured":"K\u00e4sper, E., Schwabe, P.: Faster and timing-attack resistant AES-GCM. In: Clavier, C., Gaj, K. (eds.) Cryptographic Hardware and Embedded Systems \u2013 CHES\u00a02009. LNCS, vol.\u00a05747, pp. 1\u201317. Springer, Berlin, Heidelberg (2009). https:\/\/doi.org\/10.1007\/978-3-642-04138-9_1","DOI":"10.1007\/978-3-642-04138-9_1"},{"key":"17_CR34","unstructured":"Knuth, D.E.: The Art of Computer Programming, Volume 3: Sorting and Searching, 2nd edn. Addison-Wesley, Boston (1997)"},{"key":"17_CR35","doi-asserted-by":"publisher","unstructured":"Kocher, P., et al.: Spectre attacks: exploiting speculative execution. In: 2019 IEEE Symposium on Security and Privacy, pp. 1\u201319. IEEE Computer Society Press (May 2019). https:\/\/doi.org\/10.1109\/SP.2019.00002","DOI":"10.1109\/SP.2019.00002"},{"key":"17_CR36","doi-asserted-by":"publisher","unstructured":"Kocher, P.C.: Timing attacks on implementations of Diffie-Hellman, RSA, DSS, and other systems. In: Koblitz, N. (ed.) Advances in Cryptology \u2013 CRYPTO\u201996. LNCS, vol.\u00a01109, pp. 104\u2013113. Springer, Berlin, Heidelberg (1996). https:\/\/doi.org\/10.1007\/3-540-68697-5_9","DOI":"10.1007\/3-540-68697-5_9"},{"key":"17_CR37","doi-asserted-by":"publisher","unstructured":"K\u00f6nighofer, R.: A fast and cache-timing resistant implementation of the AES. In: Malkin, T. (ed.) Topics in Cryptology \u2013 CT-RSA\u00a02008. LNCS, vol.\u00a04964, pp. 187\u2013202. Springer, Berlin, Heidelberg (2008). https:\/\/doi.org\/10.1007\/978-3-540-79263-5_12","DOI":"10.1007\/978-3-540-79263-5_12"},{"key":"17_CR38","doi-asserted-by":"publisher","unstructured":"Lemire, D.: Fast random integer generation in an interval. ACM Trans. Model. Comput. Simul. 29(1) (2019). https:\/\/doi.org\/10.1145\/3230636","DOI":"10.1145\/3230636"},{"key":"17_CR39","unstructured":"Lipp, M., et al.: Meltdown: reading kernel memory from user space. In: Enck, W., Felt, A.P. (eds.) USENIX Security 2018: 27th USENIX Security Symposium, pp. 973\u2013990. USENIX Association (2018)"},{"key":"17_CR40","doi-asserted-by":"publisher","unstructured":"Matsui, M.: How far can we go on the x64 processors? In: Robshaw, M.J.B. (ed.) Fast Software Encryption \u2013 FSE\u00a02006. LNCS, vol.\u00a04047, pp. 341\u2013358. Springer, Berlin, Heidelberg (2006). https:\/\/doi.org\/10.1007\/11799313_22","DOI":"10.1007\/11799313_22"},{"key":"17_CR41","doi-asserted-by":"publisher","unstructured":"Matsui, M., Nakajima, J.: On the power of bitslice implementation on intel core2 processor. In: Paillier, P., Verbauwhede, I. (eds.) Cryptographic Hardware and Embedded Systems \u2013 CHES\u00a02007. LNCS, vol.\u00a04727, pp. 121\u2013134. Springer, Berlin, Heidelberg (2007). https:\/\/doi.org\/10.1007\/978-3-540-74735-2_9","DOI":"10.1007\/978-3-540-74735-2_9"},{"key":"17_CR42","unstructured":"Microelectronics, S.: RM0432 reference manual: STM32L4+ series advanced Arm\u00ae-based 32-bit MCUs (2021). https:\/\/www.st.com\/resource\/en\/reference_manual\/rm0432-stm32l4-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf"},{"key":"17_CR43","doi-asserted-by":"publisher","unstructured":"Pike, R., Locanthi, B., Reiser, J.: Hardware\/software trade-offs for bitmap graphics on the blit. Softw. Pract. Exp. 15(2), 131\u2013151 (1985). https:\/\/doi.org\/10.1002\/spe.4380150203, https:\/\/onlinelibrary.wiley.com\/doi\/abs\/10.1002\/spe.4380150203","DOI":"10.1002\/spe.4380150203"},{"key":"17_CR44","unstructured":"Pornin, T.: Why constant-time crypto? (2018). https:\/\/bearssl.org\/constanttime.html"},{"key":"17_CR45","unstructured":"Pornin, T.: Falcon on ARM cortex-M4: an update. Cryptology ePrint Archive, Report 2025\/123 (2025). https:\/\/eprint.iacr.org\/2025\/123"},{"key":"17_CR46","doi-asserted-by":"publisher","unstructured":"Rodrigues, C., Oliveira, D., Pinto, S.: BUSted!!! Microarchitectural side-channel attacks on the MCU bus interconnect. In: 2024 IEEE Symposium on Security and Privacy, pp. 3679\u20133696. IEEE Computer Society Press (May 2024). https:\/\/doi.org\/10.1109\/SP54263.2024.00062","DOI":"10.1109\/SP54263.2024.00062"},{"key":"17_CR47","unstructured":"Schulman, A.: Unauthorized Windows 95: A Developer\u2019s Guide to Exploring the Foundations of Windows \u201cChicago\u201d. International Data Group Company (1994)"},{"key":"17_CR48","doi-asserted-by":"publisher","unstructured":"Schwabe, P., Stoffelen, K.: All the AES you need on Cortex-M3 and M4. In: Avanzi, R., Heys, H.M. (eds.) SAC 2016: 23rd Annual International Workshop on Selected Areas in Cryptography. NCS, vol. 10532, pp. 180\u2013194. Springer, Cham (2016). https:\/\/doi.org\/10.1007\/978-3-319-69453-5_10","DOI":"10.1007\/978-3-319-69453-5_10"},{"key":"17_CR49","unstructured":"Sendrier, N.: Secure sampling of constant-weight words \u2013 application to BIKE. Cryptology ePrint Archive, Report 2021\/1631 (2021). https:\/\/eprint.iacr.org\/2021\/1631"},{"key":"17_CR50","doi-asserted-by":"publisher","unstructured":"Tsunoo, Y., Saito, T., Suzaki, T., Shigeri, M., Miyauchi, H.: Cryptanalysis of DES implemented on computers with cache. In: Walter, C.D., Ko\u00e7, \u00c7etin Kaya., Paar, C. (eds.) Cryptographic Hardware and Embedded Systems \u2013 CHES\u00a02003. LNCS, vol.\u00a02779, pp. 62\u201376. Springer, Berlin, Heidelberg (2003). https:\/\/doi.org\/10.1007\/978-3-540-45238-6_6","DOI":"10.1007\/978-3-540-45238-6_6"},{"key":"17_CR51","unstructured":"Tsunoo, Y., Tsujihara, E., Minematsu, K., Miyauchi, H.: Cryptanalysis of block ciphers implemented on computers with cache. In: Proceedings of the International Symposium on Information Theory and Its Applications, ISITA 2002, pp. 803\u2013806 (2002)"},{"key":"17_CR52","unstructured":"Wang, Y., Paccagnella, R., He, E.T., Shacham, H., Fletcher, C.W., Kohlbrenner, D.: Hertzbleed: turning power side-channel attacks into remote timing attacks on x86. In: Butler, K.R.B., Thomas, K. (eds.) USENIX Security 2022: 31st USENIX Security Symposium, pp. 679\u2013697. USENIX Association (2022)"}],"container-title":["Lecture Notes in Computer Science","Progress in Cryptology \u2013 LATINCRYPT 2025"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-032-06754-8_17","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,1]],"date-time":"2025-10-01T08:23:18Z","timestamp":1759306998000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-032-06754-8_17"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,10,2]]},"ISBN":["9783032067531","9783032067548"],"references-count":52,"URL":"https:\/\/doi.org\/10.1007\/978-3-032-06754-8_17","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"value":"0302-9743","type":"print"},{"value":"1611-3349","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,10,2]]},"assertion":[{"value":"2 October 2025","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"LATINCRYPT","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"International Conference on Cryptology and Information Security in Latin America","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Medell\u00edn","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Colombia","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2025","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"1 October 2025","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"3 October 2025","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"9","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"latincrypt2025","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"https:\/\/ciencias.medellin.unal.edu.co\/eventos\/latincrypt\/","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}}]}}