{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,23]],"date-time":"2025-11-23T18:22:46Z","timestamp":1763922166909,"version":"3.45.0"},"publisher-location":"Cham","reference-count":12,"publisher":"Springer Nature Switzerland","isbn-type":[{"value":"9783032076113","type":"print"},{"value":"9783032076120","type":"electronic"}],"license":[{"start":{"date-parts":[[2025,11,24]],"date-time":"2025-11-24T00:00:00Z","timestamp":1763942400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2025,11,24]],"date-time":"2025-11-24T00:00:00Z","timestamp":1763942400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2026]]},"DOI":"10.1007\/978-3-032-07612-0_26","type":"book-chapter","created":{"date-parts":[[2025,11,23]],"date-time":"2025-11-23T17:57:36Z","timestamp":1763920656000},"page":"339-348","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Improving Compiler Support for\u00a0SIMD Offload Using Arm Streaming SVE"],"prefix":"10.1007","author":[{"given":"Mohamed Husain","family":"Noor Mohamed","sequence":"first","affiliation":[]},{"given":"Adarsh","family":"Patil","sequence":"additional","affiliation":[]},{"given":"Latchesar","family":"Ionkov","sequence":"additional","affiliation":[]},{"given":"Eric","family":"Van Hensbergen","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2025,11,24]]},"reference":[{"key":"26_CR1","unstructured":"LLVM 20: AArch64FrameLowering. https:\/\/github.com\/llvm\/llvm-project\/blob\/llvmorg-20.1.5\/llvm\/lib\/Target\/AArch64\/AArch64FrameLowering.cpp. Stack hazards for GPR and FPR"},{"key":"26_CR2","unstructured":"Arm: Arm 5G RAN Acceleration Library (ArmRAL). https:\/\/learn.arm.com\/learning-paths\/servers-and-cloud-computing\/ran\/. RAL library for various vector processing technologies"},{"key":"26_CR3","unstructured":"ARM: The scalable matrix extension (SME), for ARMV9-A. https:\/\/developer.arm.com\/documentation\/ddi0616\/latest\/. Arm Architecture Reference Manual Supplement"},{"key":"26_CR4","unstructured":"Arm: Streaming SVE mode. https:\/\/developer.arm.com\/documentation\/109246\/0100\/SME-Overview\/Streaming-SVE-mode"},{"key":"26_CR5","unstructured":"Arm: What is new in LLVM 20? https:\/\/community.arm.com\/arm-community-blogs\/b\/tools-software-ides-blog\/posts\/whats-new-in-llvm-20. LLVM 20"},{"key":"26_CR6","doi-asserted-by":"crossref","unstructured":"Bucek, J., Lange, K.D., v.\u00a0Kistowski, J.: SPEC CPU2017: next-generation compute benchmark. In: Companion of the 2018 ACM\/SPEC International Conference on Performance Engineering, ICPE 2018, pp. 41\u201342. Association for Computing Machinery, New York (2018). https:\/\/doi.org\/10.1145\/3185768.3185771","DOI":"10.1145\/3185768.3185771"},{"key":"26_CR7","unstructured":"Wellons, C.: Mandelbrot set in SSE, AVX, and NEON. https:\/\/github.com\/skeeto\/mandel-simd"},{"key":"26_CR8","unstructured":"Lattner, C., et al.: MLIR: a compiler infrastructure for the end of Moore\u2019s law (2020). https:\/\/arxiv.org\/abs\/2002.11054"},{"key":"26_CR9","doi-asserted-by":"publisher","unstructured":"Maleki, S., Gao, Y., Garzar\u00e1n, M.J., Wong, T., Padua, D.A.: An evaluation of vectorizing compilers. In: 2011 International Conference on Parallel Architectures and Compilation Techniques, pp. 372\u2013382 (2011). https:\/\/doi.org\/10.1109\/PACT.2011.68","DOI":"10.1109\/PACT.2011.68"},{"key":"26_CR10","doi-asserted-by":"crossref","unstructured":"Moses, W.S., Chelini, L., Zhao, R., Zinenko, O.: Polygeist: raising C to polyhedral MLIR. In: Proceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques, PACT 2021. Association for Computing Machinery, New York (2021)","DOI":"10.1109\/PACT52795.2021.00011"},{"key":"26_CR11","unstructured":"de Smalen, S.: Optimizing code for scalable vector architectures. https:\/\/llvm.org\/devmtg\/2021-11\/slides\/2021-OptimizingCodeForScalableVectorArchitectures.pdf"},{"key":"26_CR12","doi-asserted-by":"publisher","unstructured":"Wilkinson, F., McIntosh-Smith, S.: An initial evaluation of arm\u2019s scalable matrix extension. In: 2022 IEEE\/ACM International Workshop on Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems (PMBS) (2022). https:\/\/doi.org\/10.1109\/PMBS56514.2022.00018","DOI":"10.1109\/PMBS56514.2022.00018"}],"container-title":["Lecture Notes in Computer Science","High Performance Computing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-032-07612-0_26","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,11,23]],"date-time":"2025-11-23T17:57:37Z","timestamp":1763920657000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-032-07612-0_26"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,11,24]]},"ISBN":["9783032076113","9783032076120"],"references-count":12,"URL":"https:\/\/doi.org\/10.1007\/978-3-032-07612-0_26","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"value":"0302-9743","type":"print"},{"value":"1611-3349","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,11,24]]},"assertion":[{"value":"24 November 2025","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"ISC High Performance","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"International Conference on High Performance Computing","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Hamburg","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Germany","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2025","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"10 June 2025","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"13 June 2025","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"40","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"supercomputing2025","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}}]}}