{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,18]],"date-time":"2025-10-18T00:33:30Z","timestamp":1760747610697,"version":"build-2065373602"},"publisher-location":"Cham","reference-count":44,"publisher":"Springer Nature Switzerland","isbn-type":[{"value":"9783032078933","type":"print"},{"value":"9783032078940","type":"electronic"}],"license":[{"start":{"date-parts":[[2025,10,18]],"date-time":"2025-10-18T00:00:00Z","timestamp":1760745600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2025,10,18]],"date-time":"2025-10-18T00:00:00Z","timestamp":1760745600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2026]]},"DOI":"10.1007\/978-3-032-07894-0_2","type":"book-chapter","created":{"date-parts":[[2025,10,17]],"date-time":"2025-10-17T19:07:10Z","timestamp":1760728030000},"page":"23-42","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Systematic Assessment of\u00a0Cache Timing Vulnerabilities on\u00a0RISC-V Processors"],"prefix":"10.1007","author":[{"ORCID":"https:\/\/orcid.org\/0009-0002-1223-3285","authenticated-orcid":false,"given":"C\u00e9drick","family":"Austa","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5035-0576","authenticated-orcid":false,"given":"Jan Tobias","family":"M\u00fchlberg","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8539-9940","authenticated-orcid":false,"given":"Jean-Michel","family":"Dricot","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2025,10,18]]},"reference":[{"key":"2_CR1","doi-asserted-by":"publisher","unstructured":"Szefer, J.: Principles of Secure Processor Architecture Design. Springer International Publishing (2019). https:\/\/doi.org\/10.1007\/978-3-031-01760-5","DOI":"10.1007\/978-3-031-01760-5"},{"key":"2_CR2","unstructured":"Harris, S.L.: Digital Design and Computer Architecture: RISC-V edition. Morgan Kaufmann, Cambridge (2022). Includes index"},{"key":"2_CR3","unstructured":"Lipp, M., et al.: Meltdown: reading kernel memory from user space. In: 27th USENIX Security Symposium (USENIX Security 18) (2018)"},{"key":"2_CR4","doi-asserted-by":"publisher","unstructured":"Deng, S., Xiong, W., Szefer, J.: A benchmark suite for evaluating caches vulnerability to timing attacks. In: Proceedings of the 25th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 20. ACM (2020). https:\/\/doi.org\/10.1145\/3373376.3378510","DOI":"10.1145\/3373376.3378510"},{"key":"2_CR5","doi-asserted-by":"publisher","unstructured":"Rauscher, F., Fiedler, C., Kogler, A., Gruss, D.: A systematic evaluation of novel and existing cache side channels. In: Network and Distributed System Security Symposium (NDSS) 2025 (2025). https:\/\/doi.org\/10.14722\/ndss.2025.23253, https:\/\/www.ndss-symposium.org\/ndss2025\/. Network and Distributed System Security Symposium 2025 : NDSS 2025","DOI":"10.14722\/ndss.2025.23253"},{"key":"2_CR6","unstructured":"Purnal, A., Verbauwhede, I.: Cache side-channel attacks on existing and emerging computing platforms. Ph. D. thesis (2023)"},{"key":"2_CR7","doi-asserted-by":"publisher","unstructured":"Ren, X., Moody, L., Taram, M., Jordan, M., Tullsen, D.M., Venkat, A.: I see dead ops: leaking secrets via Intel\/AMD micro-op caches. In: 2021 ACM\/IEEE 48th Annual International Symposium on Computer Architecture (ISCA), pp. 361\u2013374 (2021). https:\/\/doi.org\/10.1109\/ISCA52012.2021.00036","DOI":"10.1109\/ISCA52012.2021.00036"},{"key":"2_CR8","doi-asserted-by":"publisher","unstructured":"Irazoqui, G., Eisenbarth, T., Sunar, B.: Cross processor cache attacks. In: Proceedings of the 11th ACM on Asia Conference on Computer and Communications Security, ASIA CCS 16. ACM (2016). https:\/\/doi.org\/10.1145\/2897845.2897867","DOI":"10.1145\/2897845.2897867"},{"key":"2_CR9","doi-asserted-by":"publisher","unstructured":"Lipp, M., Had\u017ei\u0107, V., Schwarz, M., Perais, A., Maurice, C., Gruss, D.: Take a way: exploring the security implications of AMD\u2019s cache way predictors. In: Proceedings of the 15th ACM Asia Conference on Computer and Communications Security, ASIA CCS 2020, pp. 813\u2013825. Association for Computing Machinery, New York, NY, USA, (2020). https:\/\/doi.org\/10.1145\/3320269.3384746","DOI":"10.1145\/3320269.3384746"},{"key":"2_CR10","unstructured":"Lipp, M., Gruss, D., Spreitzer, R., Maurice, C., Mangard, S.: ARMageddon: cache attacks on mobile devices. In: 25th USENIX Security Symposium, pp. 549\u2013564. USENIX Association (2016). https:\/\/www.usenix.org\/conference\/usenixsecurity16\/technical-sessions\/presentation\/lipp"},{"key":"2_CR11","doi-asserted-by":"crossref","unstructured":"Deng, S., Matyunin, N., Xiong, W., Katzenbeisser, S., Szefer, J.: Evaluation of cache attacks on arm processors and secure caches (2021)","DOI":"10.1109\/TC.2021.3126150"},{"key":"2_CR12","doi-asserted-by":"publisher","unstructured":"Gerlach, L., Weber, D., Zhang, R., Schwarz, M.: A security risc: microarchitectural attacks on hardware RISC-V CPUs. In: 2023 IEEE Symposium on Security and Privacy (SP), pp. 2321\u20132338 (2023). https:\/\/doi.org\/10.1109\/SP46215.2023.10179399","DOI":"10.1109\/SP46215.2023.10179399"},{"key":"2_CR13","unstructured":"Le, A.-T.: Research of RISC-V out-of-order processor cache-based side-channel attacks-systematic analysis, security models and countermeasures. Ph. D. thesis (2023)"},{"key":"2_CR14","unstructured":"Thomas, F., Hetterich, L., Zhang, R., Weber, D., Gerlach, L., Schwarz, M.: Discovering architectural CPU vulnerabilities via differential hardware fuzzing, RISCVuzz (2024)"},{"key":"2_CR15","doi-asserted-by":"publisher","unstructured":"Shuwen Deng, Wenjie Xiong, and Jakub Szefer. Analysis of secure caches using a three-step model for timing-based attacks. Journal of Hardware and Systems Security, 3 (4): 397\u2013425, November 2019. ISSN 2509-3436https:\/\/doi.org\/10.1007\/s41635-019-00075-9","DOI":"10.1007\/s41635-019-00075-9"},{"key":"2_CR16","unstructured":"Bernstein, D.J.: Cache-timing attacks on AES (2005). https:\/\/cr.yp.to\/antiforgery\/cachetiming-20050414.pdf"},{"key":"2_CR17","doi-asserted-by":"publisher","unstructured":"Bertoni, G., Zaccaria, V., Breveglieri, L., Monchiero, M., Palermo, G.: AES power attack based on induced cache miss and countermeasure. In: International Conference on Information Technology: Coding and Computing (ITCC 05) - Volume II, vol. 1, pp. 586\u2013591. IEEE (2005). https:\/\/doi.org\/10.1109\/itcc.2005.62","DOI":"10.1109\/itcc.2005.62"},{"key":"2_CR18","unstructured":"Kogler, A., et al.: Collide+power: leaking inaccessible data with software-based power side channels. In: USENIX Security (2023)"},{"key":"2_CR19","doi-asserted-by":"publisher","unstructured":"Chao, S., Zeng, Q.: Survey of CPU cache-based side-channel attacks: systematic analysis, security models, and countermeasures. Secur. Commun. Netw. 1\u201315 (2021). https:\/\/doi.org\/10.1155\/2021\/5559552. ISSN 1939\u20130114","DOI":"10.1155\/2021\/5559552"},{"key":"2_CR20","doi-asserted-by":"publisher","unstructured":"Osvik, D.A., Shamir, A., Tromer, E.: Cache Attacks and Countermeasures: The Case of AES, pp. 1\u201320. Springer Berlin Heidelberg (2006). https:\/\/doi.org\/10.1007\/11605805_1","DOI":"10.1007\/11605805_1"},{"key":"2_CR21","unstructured":"Yarom, Y., Falkner, K.: FLUSH+RELOAD: a high resolution, low noise, l3 cache side-channel attack. In: 23rd USENIX Security Symposium (USENIX Security 14), pp. 719\u2013732. USENIX Association, San Diego, CA (2014). https:\/\/www.usenix.org\/conference\/usenixsecurity14\/technical-sessions\/presentation\/yarom"},{"key":"2_CR22","unstructured":"Gruss, D., Spreitzer, R., Mangard, S.: Cache template attacks: automating attacks on inclusive last-level caches. In: 24th USENIX Security Symposium (USENIX Security 15), pp. 897\u2013912. USENIX Association, Washington, D.C. (2015). https:\/\/www.usenix.org\/conference\/usenixsecurity15\/technical-sessions\/presentation\/gruss"},{"key":"2_CR23","doi-asserted-by":"publisher","unstructured":"Gruss, D., Maurice, C., Wagner, K., Mangard, S.: Flush+Flush: A Fast and Stealthy Cache Attack, pp. 279\u2013299. Springer International Publishing (2016). https:\/\/doi.org\/10.1007\/978-3-319-40667-1_14","DOI":"10.1007\/978-3-319-40667-1_14"},{"key":"2_CR24","doi-asserted-by":"publisher","unstructured":"Gruss, D., Maurice, C., Mangard, S.: Rowhammer.js: a remote software-induced fault attack in javascript 300\u2013321 (2016). https:\/\/doi.org\/10.1007\/978-3-319-40667-1_15","DOI":"10.1007\/978-3-319-40667-1_15"},{"key":"2_CR25","unstructured":"BeagleBoard.org Foundation: BeagleV-Ahead. https:\/\/www.beagleboard.org\/boards\/beaglev-ahead. Accessed 21 Feb 2025"},{"key":"2_CR26","unstructured":"BeagleBoard.org Foundation: BeagleV-Fire. https:\/\/www.beagleboard.org\/boards\/beaglev-fire. Accessed 21 Feb 2025"},{"key":"2_CR27","unstructured":"SiFive: HiFive Unmatched. https:\/\/www.sifive.com\/boards\/hifive-unmatched. Accessed 21 Feb 2025"},{"key":"2_CR28","doi-asserted-by":"publisher","unstructured":"Kelsey, J., Schneier, B., Wagner, D., Hall, C.: Side Channel Cryptanalysis of Product Ciphers, pp. 97\u2013110. Springer Berlin Heidelberg (1998). https:\/\/doi.org\/10.1007\/bfb0055858","DOI":"10.1007\/bfb0055858"},{"key":"2_CR29","unstructured":"Page, D.: Theoretical use of cache memory as a cryptanalytic side-channel. Cryptology ePrint Archive, Paper 2002\/169 (2002). https:\/\/eprint.iacr.org\/2002\/169"},{"key":"2_CR30","unstructured":"Percival, C.: Cache missing for fun and profit (2005). https:\/\/www.daemonology.net\/hyperthreading-considered-harmful\/"},{"key":"2_CR31","doi-asserted-by":"publisher","unstructured":"Yan, M., Sprabery, R., Gopireddy, B., Fletcher, C., Campbell, R., Torrellas, J.: Attack directories, not caches: side channel attacks in a non-inclusive world. In: 2019 IEEE Symposium on Security and Privacy (SP). IEEE (2019). https:\/\/doi.org\/10.1109\/sp.2019.00004","DOI":"10.1109\/sp.2019.00004"},{"key":"2_CR32","unstructured":"Briongos, S., Malagon, P., Moya, J.M., Eisenbarth, T.: RELOAD+REFRESH: abusing cache replacement policies to perform stealthy cache attacks. In: 29th USENIX Security Symposium (USENIX Security 20), pp. 1967\u20131984. USENIX Association (2020). https:\/\/www.usenix.org\/conference\/usenixsecurity20\/presentation\/briongos"},{"key":"2_CR33","doi-asserted-by":"publisher","unstructured":"Kim, Y., et al.: Flipping bits in memory without accessing them: an experimental study of dram disturbance errors. In: 2014 ACM\/IEEE 41st International Symposium on Computer Architecture (ISCA), pp. 361\u2013372 (2014). https:\/\/doi.org\/10.1109\/ISCA.2014.6853210","DOI":"10.1109\/ISCA.2014.6853210"},{"key":"2_CR34","doi-asserted-by":"publisher","unstructured":"Liu, F., Yarom, Y., Ge, Q., Heiser, G., Lee, R.B.: Last-level cache side-channel attacks are practical. In: 2015 IEEE Symposium on Security and Privacy, pp. 605\u2013622 (2015). https:\/\/doi.org\/10.1109\/SP.2015.43","DOI":"10.1109\/SP.2015.43"},{"key":"2_CR35","unstructured":"Song, W., Liu, P.: Dynamically finding minimal eviction sets can be quicker than you think for side-channel attacks against the LLC. In: 22nd International Symposium on Research in Attacks, Intrusions and Defenses (RAID 2019), pp. 427\u2013442. USENIX Association, Beijing (2019). https:\/\/www.usenix.org\/conference\/raid2019\/presentation\/song"},{"key":"2_CR36","doi-asserted-by":"publisher","unstructured":"Vila, P., Kopf, B., Morales, J.F.: Theory and practice of finding eviction sets. In: 2019 IEEE Symposium on Security and Privacy (SP), pp. 39\u201354. IEEE (2019). https:\/\/doi.org\/10.1109\/sp.2019.00042","DOI":"10.1109\/sp.2019.00042"},{"key":"2_CR37","doi-asserted-by":"publisher","unstructured":"Lipp, M., et al.: Platypus: software-based power side-channel attacks on x86. In: 2021 IEEE Symposium on Security and Privacy (SP), pp. 355\u2013371 (2021). https:\/\/doi.org\/10.1109\/SP40001.2021.00063","DOI":"10.1109\/SP40001.2021.00063"},{"key":"2_CR38","unstructured":"Lipp, M., Gruss, D., Schwarz, M.: AMD prefetch attacks through power and time. In: 31st USENIX Security Symposium (USENIX Security 22), pp. 643\u2013660. USENIX Association, Boston, MA (2022). https:\/\/www.usenix.org\/conference\/usenixsecurity22\/presentation\/lipp"},{"issue":"1","key":"2_CR39","doi-asserted-by":"publisher","first-page":"33","DOI":"10.1007\/s41635-017-0025-y","volume":"2","author":"Y Lyu","year":"2017","unstructured":"Lyu, Y., Mishra, P.: A survey of side-channel attacks on caches and countermeasures. J. Hardware Syst. Secur. 2(1), 33\u201350 (2017). https:\/\/doi.org\/10.1007\/s41635-017-0025-y","journal-title":"J. Hardware Syst. Secur."},{"key":"2_CR40","doi-asserted-by":"publisher","unstructured":"Shen, C., Chen, C., Zhang, J.: Micro-architectural cache side-channel attacks and countermeasures. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference, ASPDAC 21, pp. 441\u2013448. ACM (2021). https:\/\/doi.org\/10.1145\/3394885.3431638","DOI":"10.1145\/3394885.3431638"},{"key":"2_CR41","doi-asserted-by":"publisher","unstructured":"Purnal, A., Giner, L., Gruss, D., Verbauwhede, I.: Systematic analysis of randomization-based protected cache architectures. In: 2021 IEEE Symposium on Security and Privacy (SP), pp. 987\u20131002. IEEE (2021). https:\/\/doi.org\/10.1109\/sp40001.2021.00011","DOI":"10.1109\/sp40001.2021.00011"},{"key":"2_CR42","doi-asserted-by":"crossref","unstructured":"Oleksenko, O., Guarnieri, M., K\u00f6pf, B., Silberstein, M.: Hide and seek with spectres: efficient discovery of speculative information leaks with random testing. In: 2023 IEEE Symposium on Security and Privacy (SP), pp. 1737\u20131752. IEEE (2023)","DOI":"10.1109\/SP46215.2023.10179391"},{"key":"2_CR43","doi-asserted-by":"crossref","unstructured":"Fabian, X., Guarnieri, M., Patrignani, M.: Automatic detection of speculative execution combinations. In: Proceedings of the 2022 ACM SIGSAC Conference on Computer and Communications Security, pp. 965\u2013978 (2022)","DOI":"10.1145\/3548606.3560555"},{"key":"2_CR44","doi-asserted-by":"crossref","unstructured":"Barthe, G., et al.: Testing side-channel security of cryptographic implementations against future microarchitectures. In: Proceedings of the 2024 on ACM SIGSAC Conference on Computer and Communications Security, pp. 1076\u20131090 (2024)","DOI":"10.1145\/3658644.3670319"}],"container-title":["Lecture Notes in Computer Science","Computer Security \u2013 ESORICS 2025"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-032-07894-0_2","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,17]],"date-time":"2025-10-17T19:07:19Z","timestamp":1760728039000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-032-07894-0_2"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,10,18]]},"ISBN":["9783032078933","9783032078940"],"references-count":44,"URL":"https:\/\/doi.org\/10.1007\/978-3-032-07894-0_2","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"value":"0302-9743","type":"print"},{"value":"1611-3349","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,10,18]]},"assertion":[{"value":"18 October 2025","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"ESORICS","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"European Symposium on Research in Computer Security","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Toulouse","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"France","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2025","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"22 September 2025","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"24 September 2025","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"30","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"esorics2025","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"https:\/\/www.esorics2025.org\/","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}}]}}