{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,12]],"date-time":"2026-01-12T10:29:55Z","timestamp":1768213795673,"version":"3.49.0"},"publisher-location":"Cham","reference-count":33,"publisher":"Springer Nature Switzerland","isbn-type":[{"value":"9783032156990","type":"print"},{"value":"9783032157003","type":"electronic"}],"license":[{"start":{"date-parts":[[2026,1,1]],"date-time":"2026-01-01T00:00:00Z","timestamp":1767225600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2026,1,1]],"date-time":"2026-01-01T00:00:00Z","timestamp":1767225600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2026]]},"DOI":"10.1007\/978-3-032-15700-3_14","type":"book-chapter","created":{"date-parts":[[2026,1,12]],"date-time":"2026-01-12T07:21:55Z","timestamp":1768202515000},"page":"287-308","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Verification of\u00a0Generic VHDL Designs and\u00a0Their Translation to\u00a0Rocq"],"prefix":"10.1007","author":[{"given":"Ocan","family":"Sankur","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Beno\u00eet","family":"Boyer","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Florian","family":"Faissole","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2026,1,13]]},"reference":[{"key":"14_CR1","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"325","DOI":"10.1007\/3-540-44798-9_26","volume-title":"Correct Hardware Design and Verification Methods","author":"C Berg","year":"2001","unstructured":"Berg, C., Jacobi, C.: Formal verification of the VAMP floating point unit. In: Margaria, T., Melham, T. (eds.) CHARME 2001. LNCS, vol. 2144, pp. 325\u2013339. Springer, Heidelberg (2001). https:\/\/doi.org\/10.1007\/3-540-44798-9_26"},{"key":"14_CR2","unstructured":"Beyer, S., Jacobi, C., Kroening, D., Leinenbach, D.: Correct hardware by synthesis from pvs. In: Submitted for Publication (2002)"},{"key":"14_CR3","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"330","DOI":"10.1007\/978-3-642-25379-9_24","volume-title":"Certified Programs and Proofs","author":"T Braibant","year":"2011","unstructured":"Braibant, T.: Coquet: a coq library for verifying hardware. In: Jouannaud, J.-P., Shao, Z. (eds.) CPP 2011. LNCS, vol. 7086, pp. 330\u2013345. Springer, Heidelberg (2011). https:\/\/doi.org\/10.1007\/978-3-642-25379-9_24"},{"key":"14_CR4","doi-asserted-by":"publisher","unstructured":"Brayton, R., Mishchenko, A.: ABC: an academic industrial-strength verification tool. In: Touili, T., Cook, B., Jackson, P. (eds.) CAV 2010. LNCS, vol. 6174, pp. 24\u201340. Springer, Heidelberg (2010). https:\/\/doi.org\/10.1007\/978-3-642-14295-6_5","DOI":"10.1007\/978-3-642-14295-6_5"},{"key":"14_CR5","doi-asserted-by":"crossref","unstructured":"Bryant, R.E.: Symbolic simulation\u2014techniques and applications. In: Proceedings of the 27th ACM\/IEEE Design Automation Conference, pp. 517\u2013521 (1991)","DOI":"10.1109\/DAC.1990.114910"},{"key":"14_CR6","doi-asserted-by":"crossref","unstructured":"Choi, J., Vijayaraghavan, M., Sherman, B., Chlipala, A., Arvind: Kami: a platform for high-level parametric hardware specification and its modular verification. Proc. ACM Program. Lang. 1(ICFP), 1\u201330 (2017)","DOI":"10.1145\/3110268"},{"key":"14_CR7","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"203","DOI":"10.1007\/3-540-59047-1_50","volume-title":"Theorem Provers in Circuit Design","author":"D Cyrluk","year":"1995","unstructured":"Cyrluk, D., Rajan, S., Shankar, N., Srivas, M.K.: Effective theorem proving for hardware verification. In: Kumar, R., Kropf, T. (eds.) TPCD 1994. LNCS, vol. 901, pp. 203\u2013222. Springer, Heidelberg (1995). https:\/\/doi.org\/10.1007\/3-540-59047-1_50"},{"key":"14_CR8","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"337","DOI":"10.1007\/978-3-540-78800-3_24","volume-title":"Tools and Algorithms for the Construction and Analysis of Systems","author":"L de Moura","year":"2008","unstructured":"de Moura, L., Bj\u00f8rner, N.: Z3: an efficient SMT solver. In: Ramakrishnan, C.R., Rehof, J. (eds.) TACAS 2008. LNCS, vol. 4963, pp. 337\u2013340. Springer, Heidelberg (2008). https:\/\/doi.org\/10.1007\/978-3-540-78800-3_24"},{"key":"14_CR9","doi-asserted-by":"publisher","unstructured":"Grumberg, O., Veith, H. (eds.): 25 Years of Model Checking. LNCS, vol. 5000. Springer, Heidelberg (2008). https:\/\/doi.org\/10.1007\/978-3-540-69850-0","DOI":"10.1007\/978-3-540-69850-0"},{"key":"14_CR10","doi-asserted-by":"publisher","first-page":"151","DOI":"10.1007\/BF00121125","volume":"1","author":"A Gupta","year":"1992","unstructured":"Gupta, A.: Formal hardware verification methods: a survey. Formal Methods Syst. Des. 1, 151\u2013238 (1992)","journal-title":"Formal Methods Syst. Des."},{"key":"14_CR11","doi-asserted-by":"crossref","unstructured":"Harrison, J.: Formal verification at intel. In: 18th Annual IEEE Symposium of Logic in Computer Science, 2003. Proceedings, pp. 45\u201354. IEEE (2003)","DOI":"10.1109\/LICS.2003.1210044"},{"key":"14_CR12","unstructured":"Huang, S.Y., Cheng, K.T.T.: Formal equivalence checking and design debugging, vol.\u00a012. Springer, Heidelberg (2012)"},{"issue":"2104","key":"14_CR13","doi-asserted-by":"publisher","first-page":"20150399","DOI":"10.1098\/rsta.2015.0399","volume":"375","author":"WA Hunt Jr","year":"2017","unstructured":"Hunt, W.A., Jr., Kaufmann, M., Moore, J.S., Slobodova, A.: Industrial hardware and software verification with ACL2. Phil. Trans. R. Soc. A: Math. Phys. Eng. Sci. 375(2104), 20150399 (2017)","journal-title":"Phil. Trans. R. Soc. A: Math. Phys. Eng. Sci."},{"key":"14_CR14","unstructured":"IEEE. IEEE standard for floating-point arithmetic. IEEE Std 754-2019 (Revision of IEEE 754-2008), pp. 1\u201384 (2019)"},{"key":"14_CR15","unstructured":"IEEE. IEEE\/IEC international standard \u2013 behavioural languages \u2013 part 1-1: VHDL language reference manual. IEC 61691-1-1:2023-10 (IEEE Std 1076-2019), pp. 1\u2013678 (2023)"},{"issue":"11","key":"14_CR16","doi-asserted-by":"publisher","first-page":"558","DOI":"10.1145\/368996.369025","volume":"5","author":"AB Kahn","year":"1962","unstructured":"Kahn, A.B.: Topological sorting of large networks. Commun. ACM 5(11), 558\u2013562 (1962)","journal-title":"Commun. ACM"},{"key":"14_CR17","unstructured":"Kaufmann, M., Russino, D.: Verification of pipeline circuits. In: ACL2 Workshop (2000)"},{"key":"14_CR18","doi-asserted-by":"crossref","unstructured":"Kuehlmann, A., Somenzi, F., Hsu, C.J., Bustan, D.: Equivalence checking. In: Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology, pp. 99\u2013130. CRC Press (2017)","DOI":"10.1201\/9781315215112-15"},{"key":"14_CR19","doi-asserted-by":"crossref","unstructured":"L\u00f6\u00f6w, A.: Lutsig: a verified verilog compiler for verified circuit development. In: Proceedings of the 10th ACM SIGPLAN International Conference on Certified Programs and Proofs, pp. 46\u201360 (2021)","DOI":"10.1145\/3437992.3439916"},{"key":"14_CR20","doi-asserted-by":"crossref","unstructured":"L\u00f6\u00f6w, A., Myreen, M.O.: A proof-producing translator for verilog development in hol. In: 2019 IEEE\/ACM 7th International Conference on Formal Methods in Software Engineering (FormaliSE), pp. 99\u2013108. IEEE (2019)","DOI":"10.1109\/FormaliSE.2019.00020"},{"key":"14_CR21","doi-asserted-by":"publisher","unstructured":"Moore, N., Lawford, M.: A case study in the automated translation of bsv hardware to pvs formal logic with subsequent verification. In: International Symposium on Theoretical Aspects of Software Engineering, pp. 65\u201372. Springer, Heidelberg (2022). https:\/\/doi.org\/10.1007\/978-3-031-10363-6_5","DOI":"10.1007\/978-3-031-10363-6_5"},{"key":"14_CR22","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"580","DOI":"10.1007\/978-3-662-49674-9_38","volume-title":"Tools and Algorithms for the Construction and Analysis of Systems","author":"R Mukherjee","year":"2016","unstructured":"Mukherjee, R., Tautschnig, M., Kroening, D.: v2c \u2013 a verilog to C translator. In: Chechik, M., Raskin, J.-F. (eds.) TACAS 2016. LNCS, vol. 9636, pp. 580\u2013586. Springer, Heidelberg (2016). https:\/\/doi.org\/10.1007\/978-3-662-49674-9_38"},{"key":"14_CR23","doi-asserted-by":"crossref","unstructured":"Pisini, V.K., Tahar, S., Curzon, P., Ait-Mohamed, O., Song, X.: Formal hardware verification by integrating hol and mdg. In: Proceedings of the 10th Great Lakes Symposium on VLSI, pp. 23\u201328 (2000)","DOI":"10.1145\/330855.330947"},{"key":"14_CR24","doi-asserted-by":"publisher","first-page":"85","DOI":"10.1007\/s11334-011-0149-0","volume":"7","author":"D Richards","year":"2011","unstructured":"Richards, D., Lester, D.: A monadic approach to automated reasoning for bluespec systemverilog. Innov. Syst. Softw. Eng. 7, 85\u201395 (2011)","journal-title":"Innov. Syst. Softw. Eng."},{"key":"14_CR25","volume-title":"Introduction to Static Analysis","author":"X Rival","year":"2020","unstructured":"Rival, X., Yi, K.: Introduction to Static Analysis. MIT Press, Boston (2020)"},{"key":"14_CR26","doi-asserted-by":"crossref","unstructured":"Russinoff, D., Bruguera, J., Chau, C., Manjrekar, M., Pfister, N., Valsaraju, H.: Formal verification of a chained multiply-add design: combining theorem proving and equivalence checking. In: 2022 IEEE 29th Symposium on Computer Arithmetic (ARITH), pp. 120\u2013126. IEEE (2022)","DOI":"10.1109\/ARITH54963.2022.00030"},{"key":"14_CR27","unstructured":"Russinoff, D., Kaufmann, M., Smith, E., Sumners, R.: Formal verification of floating-point rtl at amd using the acl2 theorem prover. In: Proceedings of the 17th IMACS World Congress on Scientific Computation, Applied Mathematics and Simulation, Paris, France (2005)"},{"key":"14_CR28","doi-asserted-by":"crossref","unstructured":"Russinoff, D.M., Flatau, A.: Rtl verification: a floating-point multiplier. In: Computer-Aided Reasoning: ACL2 Case Studies, pp. 201\u2013231. Springer, Heidelberg (2000)","DOI":"10.1007\/978-1-4757-3188-0_13"},{"key":"14_CR29","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"365","DOI":"10.1007\/3-540-55179-4_35","volume-title":"Computer Aided Verification","author":"K Schneider","year":"1992","unstructured":"Schneider, K., Kumar, R., Kropf, T.: Automating most parts of hardware proofs in HOL. In: Larsen, K.G., Skou, A. (eds.) CAV 1991. LNCS, vol. 575, pp. 365\u2013375. Springer, Heidelberg (1992). https:\/\/doi.org\/10.1007\/3-540-55179-4_35"},{"key":"14_CR30","unstructured":"Snyder, W.: Verilator 4.0: open simulation goes multithreaded. In: Open Source Digital Design Conference (ORConf) (2018)"},{"key":"14_CR31","doi-asserted-by":"crossref","unstructured":"Swords, S., Chau, C.: Robust, end-to-end correctness proofs of industrial divide and square root rtl designs. In: 2025 IEEE 32nd Symposium on Computer Arithmetic (ARITH), pp. 149\u2013156 (2025)","DOI":"10.1109\/ARITH64983.2025.00031"},{"key":"14_CR32","unstructured":"The Coq\u00a0Development Team. The coq proof assistant (2024)"},{"key":"14_CR33","doi-asserted-by":"crossref","unstructured":"Umamageswaran, K., Pandey, S.L., Wilsey, P.A.: Formal Semantics and Proof Techniques for Optimizing VHDL Models. Springer, Cham (1999)","DOI":"10.1007\/978-1-4615-5123-2"}],"container-title":["Lecture Notes in Computer Science","Verification, Model Checking, and Abstract Interpretation"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-032-15700-3_14","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,1,12]],"date-time":"2026-01-12T07:21:58Z","timestamp":1768202518000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-032-15700-3_14"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026]]},"ISBN":["9783032156990","9783032157003"],"references-count":33,"URL":"https:\/\/doi.org\/10.1007\/978-3-032-15700-3_14","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"value":"0302-9743","type":"print"},{"value":"1611-3349","type":"electronic"}],"subject":[],"published":{"date-parts":[[2026]]},"assertion":[{"value":"13 January 2026","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"VMCAI","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"International Conference on Verification, Model Checking, and Abstract Interpretation","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Rennes","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"France","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2026","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"12 January 2026","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"13 January 2026","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"27","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"vmcai2026","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"https:\/\/conf.researchr.org\/home\/VMCAI-2026","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}}]}}