{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,19]],"date-time":"2026-02-19T05:10:18Z","timestamp":1771477818950,"version":"3.50.1"},"publisher-location":"Cham","reference-count":13,"publisher":"Springer Nature Switzerland","isbn-type":[{"value":"9783032171733","type":"print"},{"value":"9783032171740","type":"electronic"}],"license":[{"start":{"date-parts":[[2026,1,1]],"date-time":"2026-01-01T00:00:00Z","timestamp":1767225600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2026,1,1]],"date-time":"2026-01-01T00:00:00Z","timestamp":1767225600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2026]]},"DOI":"10.1007\/978-3-032-17174-0_24","type":"book-chapter","created":{"date-parts":[[2026,2,19]],"date-time":"2026-02-19T04:38:14Z","timestamp":1771475894000},"page":"176-182","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Re-Architecting RISC-V: A 64-Bit Take on\u00a0Interleaved Multi-threading"],"prefix":"10.1007","author":[{"given":"Andrea","family":"Marcelli","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Marco","family":"Pisani","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rocco","family":"Martino","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Abdallah","family":"Cheikh","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Francesco","family":"Menichelli","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mauro","family":"Olivieri","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2026,2,20]]},"reference":[{"key":"24_CR1","doi-asserted-by":"crossref","unstructured":"Cardarilli, G.C., et al.: FPGA implementation of Q-RTS for real-time swarm intelligence systems. In: 2020 54th Asilomar Conference on Signals, Systems, and Computers, pp. 116\u2013120 (2020)","DOI":"10.1109\/IEEECONF51394.2020.9443368"},{"key":"24_CR2","unstructured":"Waterman, A., Lee, Y., et al.: The RISC-V Instruction Set Manual, Volume I: Unprivileged ISA. RISC-V Foundation (2024). https:\/\/github.com\/riscv\/riscv-isa-manual\/releases\/download\/20240411\/unpriv-isa-asciidoc.pdf, Accessed 18 July 2025"},{"key":"24_CR3","doi-asserted-by":"crossref","unstructured":"Cheikh, A., Cerutti, G., Mastrandrea, A., Menichelli, F., Olivieri, M.: The microarchitecture of a multi-threaded RISC-v compliant processing core family for iot end-nodes. In: International Conference on Applications in Electronics Pervading Industry, Environment and Society, pp. 89\u201397. Springer (2017)","DOI":"10.1007\/978-3-319-93082-4_12"},{"key":"24_CR4","unstructured":"Roa Logic: RV12: RISC-V Processor Soft Core. https:\/\/github.com\/RoaLogic\/RV12\/tree\/master (2025), Accessed 18 July 2025"},{"key":"24_CR5","unstructured":"OpenHW Group: cvw: CORE-V Wally RISC-V Processor Soft Core. https:\/\/github.com\/openhwgroup\/cvw\/tree\/main (2025), Accessed 18 July 2025"},{"key":"24_CR6","doi-asserted-by":"publisher","first-page":"30495","DOI":"10.1109\/ACCESS.2024.3366806","volume":"12","author":"F Vigli","year":"2024","unstructured":"Vigli, F., Barbirotta, M., Cheikh, A., Menichelli, F., Mastrandrea, A., Olivieri, M.: A risc-v fault-tolerant soft-processor based on full\/partial heterogeneous dual-core protection. IEEE Access 12, 30495\u201330506 (2024)","journal-title":"IEEE Access"},{"key":"24_CR7","doi-asserted-by":"publisher","first-page":"95720","DOI":"10.1109\/ACCESS.2024.3425579","volume":"12","author":"M Barbirotta","year":"2024","unstructured":"Barbirotta, M., Menichelli, F., Cheikh, A., Mastrandrea, A., Angioli, M., Olivieri, M.: Dynamic triple modular redundancy in interleaved hardware threads: an alternative solution to lockstep multi-cores for fault-tolerant systems. IEEE Access 12, 95720\u201395735 (2024)","journal-title":"IEEE Access"},{"key":"24_CR8","doi-asserted-by":"crossref","unstructured":"Kim, K., Harris, D., Macsai-Goren, K.: Design and synthesis of risc-v bit manipulation extensions. In: 2023 57th Asilomar Conference on Signals, Systems, and Computers, pp. 1559\u20131563 (2023)","DOI":"10.1109\/IEEECONF59524.2023.10477073"},{"issue":"2","key":"24_CR9","doi-asserted-by":"publisher","first-page":"64","DOI":"10.1109\/MM.2021.3050962","volume":"41","author":"A Cheikh","year":"2021","unstructured":"Cheikh, A., Sordillo, S., Mastrandrea, A., Menichelli, F., Scotti, G., Olivieri, M.: Klessydra-t: designing vector coprocessors for multithreaded edge-computing cores. IEEE Micro 41(2), 64\u201371 (2021)","journal-title":"IEEE Micro"},{"key":"24_CR10","doi-asserted-by":"publisher","first-page":"553","DOI":"10.1109\/OJCS.2024.3468895","volume":"5","author":"M Barbirotta","year":"2024","unstructured":"Barbirotta, M., Minervini, F., Morales, C.R., Cristal, A., Unsal, O., Olivieri, M.: Enhancing fault tolerance in high-performance computing: a real hardware case study on a risc-v vector processing unit. IEEE Open J. Comput. Soc. 5, 553\u2013565 (2024)","journal-title":"IEEE Open J. Comput. Soc."},{"key":"24_CR11","doi-asserted-by":"crossref","unstructured":"Angioli, M., Barbirotta, M., Mastrandrea, A., Jamili, S., Olivieri, M.: Automatic hardware accelerators reconfiguration through linearucb algorithms on a risc-v processor. In: 2023 18th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), pp. 169\u2013172 (2023)","DOI":"10.1109\/PRIME58259.2023.10161944"},{"issue":"7","key":"24_CR12","doi-asserted-by":"publisher","first-page":"1767","DOI":"10.1109\/TC.2024.3386060","volume":"73","author":"M Angioli","year":"2024","unstructured":"Angioli, M., et al.: Design, implementation and evaluation of a new variable latency integer division scheme. IEEE Trans. Comput. 73(7), 1767\u20131779 (2024)","journal-title":"IEEE Trans. Comput."},{"key":"24_CR13","doi-asserted-by":"crossref","unstructured":"Angioli, M., Barbirotta, M., Cheikh, A., Mastrandrea, A., Olivieri, M.: Exploring variable latency dividers in vector hardware accelerators. In: 2024 19th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), pp. 1\u20134 (2024)","DOI":"10.1109\/PRIME61930.2024.10559734"}],"container-title":["Lecture Notes in Electrical Engineering","Applications in Electronics Pervading Industry, Environment and Society"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-032-17174-0_24","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,2,19]],"date-time":"2026-02-19T04:38:18Z","timestamp":1771475898000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-032-17174-0_24"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026]]},"ISBN":["9783032171733","9783032171740"],"references-count":13,"URL":"https:\/\/doi.org\/10.1007\/978-3-032-17174-0_24","relation":{},"ISSN":["1876-1100","1876-1119"],"issn-type":[{"value":"1876-1100","type":"print"},{"value":"1876-1119","type":"electronic"}],"subject":[],"published":{"date-parts":[[2026]]},"assertion":[{"value":"20 February 2026","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"ApplePies","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"International Conference on Applications in Electronics Pervading Industry, Environment and Society","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Turin","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Italy","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2025","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"11 September 2025","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"12 September 2025","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"applepies2025","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"https:\/\/applepies.unige.it\/","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}}]}}