{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,21]],"date-time":"2026-05-21T00:09:35Z","timestamp":1779322175736,"version":"3.51.4"},"publisher-location":"Cham","reference-count":28,"publisher":"Springer Nature Switzerland","isbn-type":[{"value":"9783032238702","type":"print"},{"value":"9783032238719","type":"electronic"}],"license":[{"start":{"date-parts":[[2026,1,1]],"date-time":"2026-01-01T00:00:00Z","timestamp":1767225600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2026,1,1]],"date-time":"2026-01-01T00:00:00Z","timestamp":1767225600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2026]]},"DOI":"10.1007\/978-3-032-23871-9_3","type":"book-chapter","created":{"date-parts":[[2026,5,20]],"date-time":"2026-05-20T23:46:13Z","timestamp":1779320773000},"page":"29-41","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["MultiGRA: Expanding the\u00a0CGRA Design Space with\u00a0a\u00a0Mixed-Granularity Approach"],"prefix":"10.1007","author":[{"ORCID":"https:\/\/orcid.org\/0009-0002-5081-7695","authenticated-orcid":false,"given":"L\u00e9o","family":"Pajot","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3284-6882","authenticated-orcid":false,"given":"Quentin","family":"Dariol","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8288-2689","authenticated-orcid":false,"given":"J\u00e9r\u00e9mie","family":"Crenne","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0195-096X","authenticated-orcid":false,"given":"Simon","family":"Rokicki","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2269-8756","authenticated-orcid":false,"given":"Bertrand","family":"Le Gal","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2026,5,1]]},"reference":[{"key":"3_CR1","doi-asserted-by":"crossref","unstructured":"Akbari, O., Kamal, M., Afzali-Kusha, A., et\u00a0al.: PX-CGRA: polymorphic approximate coarse-grained reconfigurable architecture. In: Proceedings of Design, Automation & Test in Europe Conference & Exhibition (DATE) (2018)","DOI":"10.23919\/DATE.2018.8342045"},{"key":"3_CR2","doi-asserted-by":"crossref","unstructured":"Amor, H.B., Bernier, C., Prikryl, Z.: A RISC-V ISA extension for ultra-low power iot wireless signal processing. IEEE Trans. Comput. 71(4) (2022)","DOI":"10.1109\/TC.2021.3063027"},{"key":"3_CR3","doi-asserted-by":"crossref","unstructured":"Cui, E., Li, T., Wei, Q.: RISC-V instruction set architecture extensions: a survey. IEEE Access 11 (2023)","DOI":"10.1109\/ACCESS.2023.3246491"},{"key":"3_CR4","doi-asserted-by":"crossref","unstructured":"Dao, N., Attwood, A., Healy, B., Koch, D.: FlexBex: a RISC-V with a reconfigurable instruction extension. In: Proceedings of International Conference on Field-Programmable Technology (ICFPT) (2020)","DOI":"10.1109\/ICFPT51103.2020.00034"},{"key":"3_CR5","doi-asserted-by":"crossref","unstructured":"Dariol, Q., Le\u00a0Nours, S., Pillement, S., et\u00a0al.: A hybrid performance prediction approach for\u00a0fully-connected artificial neural networks on\u00a0multi-core platforms. In: Proceedings of International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) (2022)","DOI":"10.1007\/978-3-031-15074-6_16"},{"key":"3_CR6","doi-asserted-by":"crossref","unstructured":"Dave, S., Balasubramanian, M., Shrivastava, A.: RAMP: resource-aware mapping for CGRAs. In: Proceedings of Annual Design Automation Conference (2018)","DOI":"10.1145\/3195970.3196101"},{"key":"3_CR7","doi-asserted-by":"crossref","unstructured":"Fritzmann, T., Sigl, G., Sepulveda, J.: Extending the RISC-V instruction set for hardware acceleration of the post-quantum scheme LAC. In: Proceedings of Design, Automation & Test in Europe Conference & Exhibition (DATE) (2020)","DOI":"10.23919\/DATE48585.2020.9116567"},{"key":"3_CR8","doi-asserted-by":"crossref","unstructured":"Gautschi, M., Schiavone, P.D., Traber, A., et\u00a0al.: Near-threshold RISC-V core with DSP extensions for scalable IoT endpoint devices. IEEE Trans. Very Large Scale Integrat. (VLSI) Syst. 25(10) (2017)","DOI":"10.1109\/TVLSI.2017.2654506"},{"key":"3_CR9","doi-asserted-by":"crossref","unstructured":"Gobieski, G., Ghosh, S., Heule, M., et\u00a0al.: RipTide: a programmable, energy-minimal dataflow compiler and architecture. In: Proceedings of International Symposium on Microarchitecture (MICRO) (2022)","DOI":"10.1109\/MICRO56248.2022.00046"},{"key":"3_CR10","doi-asserted-by":"crossref","unstructured":"Jiao, Q., Hu, W., Liu, F., et\u00a0al.: RISC-VTF: RISC-V based extended instruction set for transformer. In: Proceedings of International Conference on Systems, Man, and Cybernetics (SMC) (2021)","DOI":"10.1109\/SMC52423.2021.9658643"},{"key":"3_CR11","doi-asserted-by":"crossref","unstructured":"Juneja, R., Dangi, P., Bandara, T.K., et\u00a0al.: Building an open CGRA ecosystem for agile innovation (2025)","DOI":"10.1109\/ICCAD66269.2025.11240628"},{"key":"3_CR12","doi-asserted-by":"crossref","unstructured":"Koch, D., Dao, N., Healy, B., et\u00a0al.: FABulous: an embedded FPGA framework. In: Proceedings of International Symposium on Field-Programmable Gate Arrays (2021)","DOI":"10.1145\/3431920.3439302"},{"key":"3_CR13","doi-asserted-by":"crossref","unstructured":"Le, V.T.D., Pham, H.L., Tran, T.H., et\u00a0al.: Efficient and high-speed CGRA accelerator for cryptographic applications. In: Proceedings of Eleventh International Symposium on Computing and Networking (CANDAR) (2023)","DOI":"10.1109\/CANDAR60563.2023.00033"},{"key":"3_CR14","doi-asserted-by":"crossref","unstructured":"Li, A., Ning, A., Wentzlaff, D.: Duet: creating harmony between processors and embedded FPGAs. In: Proceedings of International Symposium on High-Performance Computer Architecture (HPCA) (2023)","DOI":"10.1109\/HPCA56546.2023.10070989"},{"key":"3_CR15","doi-asserted-by":"crossref","unstructured":"Li, A., Wentzlaff, D.: PRGA: an open-source FPGA research and prototyping framework. In: Proceedings of Symposium on Field-Programmable Gate Arrays (2021)","DOI":"10.1145\/3431920.3439294"},{"key":"3_CR16","doi-asserted-by":"crossref","unstructured":"Liu, L., et al.: A survey of coarse-grained reconfigurable architecture and design: taxonomy, challenges, and applications. ACM Comput. Surv. 52(6) (2020)","DOI":"10.1145\/3357375"},{"key":"3_CR17","doi-asserted-by":"crossref","unstructured":"Martin, K.J.M.: Twenty years of automated methods for mapping applications on CGRA. In: Proceedings of International Parallel and Distributed Processing Symposium Workshops (IPDPSW) (2022)","DOI":"10.1109\/IPDPSW55747.2022.00118"},{"key":"3_CR18","unstructured":"Mei, B., Berekovic, M., Mignolet, J.Y.: ADRES & DRESC: architecture and compiler for coarse-grain reconfigurable processors. In: Vassiliadis, S., Soudris, D. (eds.) Fine- and Coarse-Grain Reconfigurable Computing (2007)"},{"key":"3_CR19","doi-asserted-by":"crossref","unstructured":"Park, Y., Park, H., Mahlke, S.: CGRA express: accelerating execution using dynamic operation fusion. In: Proceedings of International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (2009)","DOI":"10.1145\/1629395.1629433"},{"key":"3_CR20","doi-asserted-by":"crossref","unstructured":"Prabhakar, R., Zhang, Y., Koeplinger, D., et\u00a0al.: Plasticine: a reconfigurable architecture for parallel patterns. In: Proceedings of Annual International Symposium on Computer Architecture (2017)","DOI":"10.1145\/3079856.3080256"},{"key":"3_CR21","doi-asserted-by":"crossref","unstructured":"Prasad, R., Das, S., Martin, K.J.M., et\u00a0al.: Floating point CGRA based ultra-low power DSP accelerator. J. Sign. Process. Syst. 93(10) (2021)","DOI":"10.1007\/s11265-020-01630-2"},{"key":"3_CR22","doi-asserted-by":"crossref","unstructured":"Ragheb, O., et\u00a0al.: CGRA-ME 2.0: a research framework for next-generation CGRA architectures and CAD. In: Proceedings of International Parallel and Distributed Processing Symposium Workshops (IPDPSW) (2024)","DOI":"10.1109\/IPDPSW63119.2024.00124"},{"key":"3_CR23","doi-asserted-by":"crossref","unstructured":"Sankaralingam, K., et al.: TRIPS: a polymorphous architecture for exploiting ILP, TLP, and DLP. ACM Trans. Archit. Code Optim. (2004)","DOI":"10.1145\/980152.980156"},{"key":"3_CR24","unstructured":"Swanson, S., Michelson, K., Schwerin, A., et\u00a0al.: WaveScalar. In: Procedings of Digital Avionics Systems Conference (2003)"},{"key":"3_CR25","doi-asserted-by":"crossref","unstructured":"Tan, C., Agostini, N.B., Zhang, J., et\u00a0al.: OpenCGRA: democratizing coarse-grained reconfigurable arrays. In: Proceedings of International Conference on Application-specific Systems, Architectures and Processors (ASAP) (2021)","DOI":"10.1109\/ASAP52443.2021.00029"},{"key":"3_CR26","doi-asserted-by":"crossref","unstructured":"Tang, X., Giacomin, E., Chauviere, B., et\u00a0al.: OpenFPGA: an open-source framework for agile prototyping customizable FPGAs. IEEE Micro 40(4) (2020)","DOI":"10.1109\/MM.2020.2995854"},{"key":"3_CR27","unstructured":"Waterman, A., Asanovi\u0107, K.: The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Document Version 20191214-draft (2019)"},{"key":"3_CR28","doi-asserted-by":"crossref","unstructured":"Wijtvliet, M., Waeijen, L., Corporaal, H.: Coarse grained reconfigurable architectures in the past 25 years: overview and classification. In: Proceedings of International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) (2016)","DOI":"10.1109\/SAMOS.2016.7818353"}],"container-title":["Lecture Notes in Computer Science","Design and Architecture for Signal and Image Processing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-032-23871-9_3","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,5,20]],"date-time":"2026-05-20T23:46:18Z","timestamp":1779320778000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-032-23871-9_3"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026]]},"ISBN":["9783032238702","9783032238719"],"references-count":28,"URL":"https:\/\/doi.org\/10.1007\/978-3-032-23871-9_3","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"value":"0302-9743","type":"print"},{"value":"1611-3349","type":"electronic"}],"subject":[],"published":{"date-parts":[[2026]]},"assertion":[{"value":"1 May 2026","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"DASIP","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"International Workshop on Design and Architectures for Signal and Image Processing","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Krakow","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Poland","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2026","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"26 January 2026","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"28 January 2026","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"19","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"dasip2026","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"https:\/\/dasip-2026.github.io\/","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}}]}}