{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,8,14]],"date-time":"2026-08-14T10:30:22Z","timestamp":1786703422858,"version":"build-2736575974"},"publisher-location":"Cham","reference-count":18,"publisher":"Springer Nature Switzerland","isbn-type":[{"value":"9783032352477","type":"print"},{"value":"9783032352484","type":"electronic"}],"license":[{"start":{"date-parts":[[2026,8,15]],"date-time":"2026-08-15T00:00:00Z","timestamp":1786752000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2026,8,15]],"date-time":"2026-08-15T00:00:00Z","timestamp":1786752000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2027]]},"DOI":"10.1007\/978-3-032-35248-4_8","type":"book-chapter","created":{"date-parts":[[2026,8,14]],"date-time":"2026-08-14T09:43:51Z","timestamp":1786700631000},"page":"106-120","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Closer in the Gap: Towards Portable Performance on RISC-V Vector Processors"],"prefix":"10.1007","author":[{"ORCID":"https:\/\/orcid.org\/0009-0003-4387-367X","authenticated-orcid":false,"given":"Ruimin","family":"Shi","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4229-5735","authenticated-orcid":false,"given":"Maya","family":"Gokhale","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4977-814X","authenticated-orcid":false,"given":"Pei-Hung","family":"Lin","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5181-7545","authenticated-orcid":false,"given":"Xavier","family":"Teruel","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4158-3583","authenticated-orcid":false,"given":"Ivy","family":"Peng","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"297","published-online":{"date-parts":[[2026,8,15]]},"reference":[{"issue":"5","key":"8_CR1","doi-asserted-by":"publisher","first-page":"41","DOI":"10.1109\/MM.2022.3184867","volume":"42","author":"N Adit","year":"2022","unstructured":"Adit, N., Sampson, A.: Performance left on the table: an evaluation of compiler autovectorization for RISC-V. IEEE Micro 42(5), 41\u201348 (2022)","journal-title":"IEEE Micro"},{"key":"8_CR2","unstructured":"Asanovic., K.: https:\/\/github.com\/riscv\/riscv-v-spec\/releases\/tag\/v1.0 (2021)"},{"key":"8_CR3","doi-asserted-by":"crossref","unstructured":"Banchelli, F.: RISC-V in HPC: a look into tools for performance monitoring. In: International Conference on High Performance Computing, pp. 562\u2013575 (2025)","DOI":"10.1007\/978-3-032-07612-0_43"},{"key":"8_CR4","unstructured":"Bernstein, O.: RISC-V Vector benchmark. https:\/\/github.com\/camel-cdr\/rvv-bench"},{"key":"8_CR5","doi-asserted-by":"crossref","unstructured":"Brown, N.: Is RISC-V ready for HPC prime-time: evaluating the 64-core sophon SG2042 RISC-V CPU. In: Proceedings of the SC\u201923 Workshops, pp. 1566\u20131574 (2023)","DOI":"10.1145\/3624062.3624234"},{"key":"8_CR6","doi-asserted-by":"crossref","unstructured":"Carpentieri: A performance analysis of autovectorization on RVV RISC-V boards. In: Proceedings of the PDP, pp. 129\u2013136 (2025)","DOI":"10.1109\/PDP66500.2025.00026"},{"key":"8_CR7","doi-asserted-by":"crossref","unstructured":"Garcia, A.M.: Inference performance of large language models on a 64-core RISC-V CPU with silicon-enabled vectors. Future Gener. Comput. Syst. 108242 (2025)","DOI":"10.1016\/j.future.2025.108242"},{"key":"8_CR8","doi-asserted-by":"crossref","unstructured":"Gupta, S.R.: Accelerating CNN inference on long vector architectures via co-design. In: 2023 IEEE International Parallel and Distributed Processing Symposium, pp. 145\u2013155. IEEE (2023)","DOI":"10.1109\/IPDPS54959.2023.00024"},{"key":"8_CR9","doi-asserted-by":"crossref","unstructured":"Lai, H.M.: RISC-V vectorization coverage for HPC: a TSVC-based analysis. In: Proceedings of the SC\u201925 Workshops, pp. 1676\u20131683 (2025)","DOI":"10.1145\/3731599.3767535"},{"key":"8_CR10","doi-asserted-by":"publisher","unstructured":"Lee, J.K.: Test-driving RISC-V vector hardware for HPC. In: Bienz, A., Weiland, M., Baboulin, M., Kruse, C. (eds.) International Conference on High Performance Computing, pp. 419\u2013432. Springer, Cham (2023). https:\/\/doi.org\/10.1007\/978-3-031-40843-4_31","DOI":"10.1007\/978-3-031-40843-4_31"},{"key":"8_CR11","doi-asserted-by":"crossref","unstructured":"Lin, J.K.: Rewriting and optimizing vector length agnostic intrinsics from arm SVE to RVV. In: Proceedings of the 53rd ICPP Workshops, pp. 38\u201347 (2024)","DOI":"10.1145\/3677333.3678151"},{"key":"8_CR12","doi-asserted-by":"crossref","unstructured":"Peccia, F.N., Haxel, F., Bringmann, O.: Tensor program optimization for the RISC-V vector extension using probabilistic programs. In: 2025 IEEE\/ACM International Conference On Computer Aided Design (ICCAD), pp. 1\u20139. IEEE (2025)","DOI":"10.1109\/ICCAD66269.2025.11241007"},{"key":"8_CR13","doi-asserted-by":"crossref","unstructured":"Perotti, M., et al.: A \u201cnew ara\u201d for vector computing: an open source highly efficient RISC-V V 1.0 vector processor design. In: ASAP. IEEE (2022)","DOI":"10.1109\/ASAP54787.2022.00017"},{"key":"8_CR14","doi-asserted-by":"publisher","unstructured":"Quantum AI team: QSIM (2025). https:\/\/doi.org\/10.5281\/zenodo.4067237","DOI":"10.5281\/zenodo.4067237"},{"issue":"4","key":"8_CR15","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/3422667","volume":"17","author":"C Ram\u00edrez","year":"2020","unstructured":"Ram\u00edrez, C., et al.: A RISC-V simulator and benchmark suite for designing and evaluating vector architectures. TACO 17(4), 1\u201330 (2020)","journal-title":"TACO"},{"key":"8_CR16","doi-asserted-by":"publisher","unstructured":"Shi, R., Schieffer, G., Gokhale, M., Lin, P.H., Patel, H., Peng, I. : ARM SVE unleashed: performance and insights across HPC applications on nvidia grace. In: Nagel, W.E., Goehringer, D., Diniz, P.C. (eds.) European Conference on Parallel Processing, pp. 33\u201347. Springer, Cham (2025). https:\/\/doi.org\/10.1007\/978-3-031-99857-7_3","DOI":"10.1007\/978-3-031-99857-7_3"},{"key":"8_CR17","doi-asserted-by":"crossref","unstructured":"Shi, R., et al.: High-performance vector-length agnostic quantum circuit simulations on arm processors. In: International Parallel and Distributed Processing Symposium. IEEE (2026)","DOI":"10.1109\/IPDPS65963.2026.00080"},{"key":"8_CR18","doi-asserted-by":"crossref","unstructured":"Vizcaino, P., et al.: Designing a QEMU plugin to profile multicore long vector RISC-V architectures: rave. Future Gener. Comput. Syst. 108100 (2025)","DOI":"10.2139\/ssrn.5147912"}],"container-title":["Lecture Notes in Computer Science","Euro-Par 2026: Parallel Processing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-032-35248-4_8","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,8,14]],"date-time":"2026-08-14T09:43:55Z","timestamp":1786700635000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-032-35248-4_8"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,8,15]]},"ISBN":["9783032352477","9783032352484"],"references-count":18,"URL":"https:\/\/doi.org\/10.1007\/978-3-032-35248-4_8","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"value":"0302-9743","type":"print"},{"value":"1611-3349","type":"electronic"}],"subject":[],"published":{"date-parts":[[2026,8,15]]},"assertion":[{"value":"15 August 2026","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"The authors have no competing interests to declare that are relevant to the content of this article.","order":1,"name":"Ethics","label":"Disclosure of Interests","group":{"name":"EthicsHeading","label":"Ethics"}},{"value":"Euro-Par","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"European Conference on Parallel Processing","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Pisa","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Italy","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2026","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"24 August 2026","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"28 August 2026","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"32","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"europar2026","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"https:\/\/2026.euro-par.org\/","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}}]}}