{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,27]],"date-time":"2025-03-27T17:53:27Z","timestamp":1743098007816,"version":"3.40.3"},"publisher-location":"Cham","reference-count":19,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783319162133"},{"type":"electronic","value":"9783319162140"}],"license":[{"start":{"date-parts":[[2015,1,1]],"date-time":"2015-01-01T00:00:00Z","timestamp":1420070400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2015,1,1]],"date-time":"2015-01-01T00:00:00Z","timestamp":1420070400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015]]},"DOI":"10.1007\/978-3-319-16214-0_23","type":"book-chapter","created":{"date-parts":[[2015,3,30]],"date-time":"2015-03-30T22:56:39Z","timestamp":1427756199000},"page":"280-290","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":3,"title":["The Effects of System Hyper Pipelining on Three Computational Benchmarks Using FPGAs"],"prefix":"10.1007","author":[{"given":"Tobias","family":"Strauch","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2015,3,31]]},"reference":[{"key":"23_CR1","unstructured":"Abdelfattah, M.S., Betz, V.: The power of communication: Energy- efficient NoCs for FPGAs. In: Intern. Conf. on FPL, pp. 1\u20138. Porto, Portugal September 2-4, 2013"},{"key":"23_CR2","doi-asserted-by":"crossref","unstructured":"Matthews, E., Shannon, L., Dedorova, A.: Polyblaze: from one to many. Bringing the microblaze into the multicore era with linux SMP support. In: 22nd Intern. Conf. On FPL, pp. 224\u2013230. Oslo, Norway August 29-31, 2012","DOI":"10.1109\/FPL.2012.6339185"},{"key":"23_CR3","unstructured":"Vallina, F.M., Jachimiec, N., Saniie, J.: Multiprocessor and operating system design for signal processing on an FPGA. In: IEEE Intl. Conf. on Electro\/ Information Technology, pp. 378\u2013383. Chicago, IL, USA May 17-20, 2007"},{"key":"23_CR4","doi-asserted-by":"crossref","unstructured":"Klimm, A., Braun, L., Becker, J.: An adaptive and scalable multiprocessor system for xilinx FPGAs using minimal sized processor cores. In: IEEE Inter. Symposium on Parallel and Ditributed Processing, pp. 1\u20137. Miami, Fl, USA April 14-18, 2008","DOI":"10.1109\/IPDPS.2008.4536519"},{"key":"23_CR5","doi-asserted-by":"crossref","unstructured":"Wallentowitz, S., Lankes, A., Zaib, A., Wild, T., Herkersdorf, A.: A framework for open tiled manycore system-on-chip. In: 22nd Intern. Conf. on FPL, pp.535\u2013538. Oslo, Norway August 29-31, 2012","DOI":"10.1109\/FPL.2012.6339273"},{"key":"23_CR6","doi-asserted-by":"crossref","unstructured":"Henrey, M., Edmond, S., Shannon, L., Menon, C.: Bio-inspired walking: A FPGA multicore system for a legged robot. In: 22nd Inter. Conf. on FPL, pp. 105\u2013111. Oslo, Norway August 29-31, 2012","DOI":"10.1109\/FPL.2012.6339248"},{"key":"23_CR7","doi-asserted-by":"crossref","unstructured":"Lu, Y., Sezer, S., McCanny, J.: Advanced multithreading architecture with hardware based thread scheduling. In: Inter. Conf. on FPL, pp. 95\u2013100. Milano, Italy 31 August \u20132 September 2010","DOI":"10.1109\/FPL.2010.28"},{"key":"23_CR8","doi-asserted-by":"crossref","unstructured":"Tatas, K., Kyriacou, C.: Implementation of a threaded dataflow multiprocessor using FPGA. In: 6th Intern. Conf. on DTIS, pp. 1\u20136. Athens, Greece April 6-8, 2011","DOI":"10.1109\/DTIS.2011.5941444"},{"key":"23_CR9","doi-asserted-by":"crossref","unstructured":"Labrecque, M., Steffan, J.G.: Improving pipelined soft processors with multitherading. In: Intern. Conf. on FPL, pp. 210\u2013215. Amsterdam August 27-29, 2007","DOI":"10.1109\/FPL.2007.4380649"},{"key":"23_CR10","doi-asserted-by":"crossref","unstructured":"Labrecque, M., Steffan, J.G.: Fast critical sections via thread scheduling for FPGA-based multithreaded processors. In: Intern. Conf. on FPL, pp. 18\u201325. Prague, Czech Republic 31 August \u20132 September 2009","DOI":"10.1109\/FPL.2009.5272561"},{"issue":"1","key":"23_CR11","doi-asserted-by":"publisher","first-page":"5","DOI":"10.1007\/BF01759032","volume":"6","author":"C Leiserson","year":"1991","unstructured":"Leiserson, C., Saxe, J.: Retiming Synchronous Circuitry. Algorithmica 6(1), 5\u201335 (1991)","journal-title":"Algorithmica"},{"key":"23_CR12","unstructured":"Weaver, N., Wawrzynek, J.: The effects of datapath placement and C- slow retiming on three computational benchmarks. In: Proc. FCCM 2002, pp. 303\u2013304. Napa, CA, USA April 24, 2002"},{"key":"23_CR13","unstructured":"Strauch, T.: Timing driven C-slow retiming on RTL for multicores on FPGAs. In: ParaFPGA 2013. Munich, Germany September 10-13, 2013. www.edaptix.com\/ParCo2013_Strauch_CSR_RTL.pdf"},{"key":"23_CR14","doi-asserted-by":"crossref","unstructured":"Su, M., Zhou, L., Shi, C.: Maximizing the throughput-area efficiency of fully-parallel low-density parity-check decoding with c-slow retiming and asynchronous deep pipelining. In: ICCD 2007, pp. 636\u2013643. Lake Tahoe, CA, USA October 7-10, 2007","DOI":"10.1109\/ICCD.2007.4601964"},{"key":"23_CR15","unstructured":"Afram, M., Khan, A., Sarfaraz, M.: C-slow technique vs. multiprocessor in designing low area customized set processor for embedded applications. In: Intern. Journal of Computer Applications 6(7) (2001)"},{"key":"23_CR16","doi-asserted-by":"crossref","unstructured":"Cadenas, J., Sherratt, S., Huerta, P., Kao, W.-C., Megson, G.M.: C-slow retimed parallel histogram archi-tectures for consumer imaging devices. Transactions on Consumer Electronics 59(2), pp. 291\u2013295","DOI":"10.1109\/TCE.2013.6531108"},{"key":"23_CR17","unstructured":"Opencores, Stockholm, Sweden, 2007. www.opencores.org\/projects"},{"key":"23_CR18","unstructured":"The RISCV Instruction Set Architecture (riscv.org)"},{"key":"23_CR19","unstructured":"Atmel: AT91SAM ARM based Flashed MCU. http:\/\/www.atmel.com\/Images\/doc11057.pdf"}],"container-title":["Lecture Notes in Computer Science","Applied Reconfigurable Computing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-319-16214-0_23","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,1,20]],"date-time":"2023-01-20T16:09:42Z","timestamp":1674230982000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-319-16214-0_23"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015]]},"ISBN":["9783319162133","9783319162140"],"references-count":19,"URL":"https:\/\/doi.org\/10.1007\/978-3-319-16214-0_23","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2015]]},"assertion":[{"value":"31 March 2015","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}}]}}