{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,29]],"date-time":"2025-05-29T05:40:01Z","timestamp":1748497201924,"version":"3.41.0"},"publisher-location":"Cham","reference-count":59,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783319200705"},{"type":"electronic","value":"9783319200712"}],"license":[{"start":{"date-parts":[[2015,1,1]],"date-time":"2015-01-01T00:00:00Z","timestamp":1420070400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2015,1,1]],"date-time":"2015-01-01T00:00:00Z","timestamp":1420070400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015]]},"DOI":"10.1007\/978-3-319-20071-2_3","type":"book-chapter","created":{"date-parts":[[2015,7,14]],"date-time":"2015-07-14T07:20:48Z","timestamp":1436858448000},"page":"69-96","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["Design Intelligence for Interconnection Realization in Power-Managed SoCs"],"prefix":"10.1007","author":[{"given":"Houman","family":"Zarrabi","sequence":"first","affiliation":[]},{"given":"A. J.","family":"Al-Khalili","sequence":"additional","affiliation":[]},{"given":"Yvon","family":"Savaria","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2015,7,15]]},"reference":[{"key":"3_CR1","doi-asserted-by":"crossref","unstructured":"Martin, G.: Overview of the MPSoC design challenge. In: Proceedings of the 43rd Annual Design Automation Conference, July 2006","DOI":"10.1145\/1146909.1146980"},{"key":"3_CR2","unstructured":"Horowitz, M., Indermaur, T., Gonzalez, R.: Low-power digital design. In: Symposium on low power electronics (1994)"},{"key":"3_CR3","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-5455-4","volume-title":"Dynamic Power Management: Design Techniques and CAD Tools","author":"L Benini","year":"1998","unstructured":"Benini, L., Micheli, G.D.: Dynamic Power Management: Design Techniques and CAD Tools. Kluwer Academic Publishers, Massachusetts (1998)"},{"key":"3_CR4","doi-asserted-by":"crossref","unstructured":"Burd, T.D., Brodersen, R.W.: Design issues for dynamic voltage scaling. In: Proceedings of the 2000 International Symposium on Low Power Electronics and Design, July 2000","DOI":"10.1145\/344166.344181"},{"issue":"3","key":"3_CR5","doi-asserted-by":"publisher","first-page":"299","DOI":"10.1109\/92.845896","volume":"8","author":"L Benini","year":"2000","unstructured":"Benini, L., Bogliolo, A., De Micheli, G.: A survey of design techniques for system-level dynamic power management. IEEE Trans. Very Large Scale Integr. Syst. 8(3), 299\u2013316 (2000)","journal-title":"IEEE Trans. Very Large Scale Integr. Syst."},{"key":"3_CR6","doi-asserted-by":"crossref","unstructured":"Pontes, J., Moreira, M., Soares, R., Calazans, N.: Hermes-GLP: a GALS network on chip router with power control techniques. In: Proceedings of the International Symposium on VLSI (ISVLI) (2008)","DOI":"10.1109\/ISVLSI.2008.90"},{"key":"3_CR7","unstructured":"Semeraro, G., Magklis, G., Balasubramonian, R., Albonesi, D.H., Dwarkadas, S., Scott, M.L.: Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling. In: HPCA (2002)"},{"key":"3_CR8","doi-asserted-by":"crossref","unstructured":"Chen, G., Li, F., Kandemir, M., Irwin, M.: Reducing NoC energy consumption through compiler-directed channel voltage scaling. SIGPLAN Not. 41, 6, June (2006)","DOI":"10.1145\/1133255.1134004"},{"key":"3_CR9","doi-asserted-by":"crossref","unstructured":"Li, F., Chen, G., Kandemir, M., Kolcu, I.: Profile-driven energy reduction in network-on-chips. SIGPLAN Not. 42, 6, June (2007)","DOI":"10.1145\/1273442.1250779"},{"issue":"4","key":"3_CR10","doi-asserted-by":"publisher","first-page":"23","DOI":"10.1109\/40.782564","volume":"19","author":"S Borkar","year":"1999","unstructured":"Borkar, S.: Design challenges of technology scaling. IEEE Micro 19(4), 23\u201329 (1999)","journal-title":"IEEE Micro"},{"key":"3_CR11","doi-asserted-by":"publisher","first-page":"649","DOI":"10.1109\/92.902259","volume":"8","author":"P Zarkesh-Ha","year":"2000","unstructured":"Zarkesh-Ha, P., Davis, J.A., Meindl, J.D.: Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip. IEEE Trans. Very Large Scale Integr. Syst. 8, 649\u2013659 (2000)","journal-title":"IEEE Trans. Very Large Scale Integr. Syst."},{"key":"3_CR12","doi-asserted-by":"crossref","unstructured":"Magen, N., Kolodny, A., Weiserm, U., Shamir, N.: Interconnect-power dissipation in a microprocessor. In: Proceedings of the International Workshop on System Level Interconnect Prediction, February (2004)","DOI":"10.1145\/966747.966750"},{"key":"3_CR13","doi-asserted-by":"crossref","unstructured":"Lackey, D.E., Zuchowski, P.S., Bednar, T.R., Stout, D.W., Gould, S.W., Cohn, J.M.: Managing power and performance for system-on-chip designs using Voltage Islands. In: ICCAD (2002)","DOI":"10.1145\/774572.774601"},{"key":"3_CR14","unstructured":"Semeraro, G., Albonesi, D.H., Dropsho, S.G., Magklis, G., Dwarkadas, S., Scott, M.L.: Dynamic frequency and voltage control for a multiple clock domain microarchitecture. ACM\/IEEE International Symposium on Microarchitecture (2003)"},{"key":"3_CR15","doi-asserted-by":"crossref","unstructured":"Magklis, G., Scott, M.L., Semeraro, G., Albonesi, D.H., Dropsho, S.: Profile-based dynamic voltage and frequency scaling for a multiple clock domain microprocessor. In: ISCA (2003)","DOI":"10.1145\/859618.859621"},{"key":"3_CR16","doi-asserted-by":"crossref","unstructured":"Bakoglu, H.B., Meindl, J.D.: Optimal interconnection circuits for VLSI. IEEE Trans. Electron Devices ED-32, 903\u2013909 (1985)","DOI":"10.1109\/T-ED.1985.22046"},{"key":"3_CR17","unstructured":"Nalamalpu, A., Burleson, W.: A practical approach to DSM repeater insertion: Satisfying delay constraints while minimizing area and power. In: IEEE ASIC\/SOC Conference, September (2001)"},{"key":"3_CR18","unstructured":"Chen, G., Friedman, E.G.: Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints. In: IEEE TVLSI, February (2006)"},{"key":"3_CR19","unstructured":"Kaul, H., Sylvester, D., Blaauw, D., Mudge, T., Austin, T.: DVS for on-chip bus designs based on timing error correction. DATE, March (2005)"},{"issue":"11","key":"3_CR20","first-page":"2001","volume":"49","author":"K Banerjee","year":"2002","unstructured":"Banerjee, K., Mehrotra, A.: A power-optimal repeater insertion methodology for global interconnects in nanometer designs. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 49(11), 2001\u20132007 (2002)","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"issue":"1","key":"3_CR21","doi-asserted-by":"publisher","first-page":"50","DOI":"10.1109\/43.974137","volume":"21","author":"A Nalamalpu","year":"2002","unstructured":"Nalamalpu, A., Srinivasan, S., Burleson, W.P.: Boosters for driving long onchip interconnects-design issues, interconnect synthesis, and comparison with repeaters. IEEE Trans Comput.-Aided Des. 21(1), 50\u201362 (2002)","journal-title":"IEEE Trans Comput.-Aided Des."},{"issue":"11","key":"3_CR22","doi-asserted-by":"publisher","first-page":"1633","DOI":"10.1109\/43.806808","volume":"18","author":"C Alpert","year":"1999","unstructured":"Alpert, C., Devgan, A., Quay, S.: Buffer insertion for noise and delay optimization. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 18(11), 1633\u20131645 (1999)","journal-title":"IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."},{"key":"3_CR23","doi-asserted-by":"crossref","unstructured":"van Ginneken, L.P.P.P.: Buffer placement in distributed RC-tree networks for minimal elmore delay. In: Proceedings of the International Symposium Circuits System (ISCAS), pp. 865\u2013868 (1990)","DOI":"10.1109\/ISCAS.1990.112223"},{"issue":"5","key":"3_CR24","doi-asserted-by":"publisher","first-page":"607","DOI":"10.1109\/82.673643","volume":"45","author":"V Adler","year":"1998","unstructured":"Adler, V., Friedman, E.G.: Repeater design to reduce delay and power in resistive interconnect. IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process. 45(5), 607\u2013616 (1998)","journal-title":"IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process."},{"issue":"2","key":"3_CR25","doi-asserted-by":"publisher","first-page":"195","DOI":"10.1109\/92.831439","volume":"8","author":"YI Ismail","year":"2000","unstructured":"Ismail, Y.I., Friedman, E.G.: Effects of inductance on the propagation delay and repeater insertion in VLSI circuits. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 8(2), 195\u2013206 (2000)","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"issue":"9","key":"3_CR26","doi-asserted-by":"publisher","first-page":"1230","DOI":"10.1109\/TVLSI.2008.2000861","volume":"16","author":"CJ Akl","year":"2008","unstructured":"Akl, C.J., Bayoumi, M.A.: Reducing interconnect delay uncertainty via hybrid polarity repeater insertion. IEEE Trans. Very Large Scale Integr. Syst. 16(9), 1230\u20131239 (2008)","journal-title":"IEEE Trans. Very Large Scale Integr. Syst."},{"issue":"11","key":"3_CR27","doi-asserted-by":"publisher","first-page":"1239","DOI":"10.1109\/TVLSI.2005.859588","volume":"13","author":"B Zhai","year":"2005","unstructured":"Zhai, B., Blaauw, D., Sylvester, D., Flautner, K.: The limit of dynamic voltage scaling and insomniac dynamic voltage scaling. Trans. VLSI 13(11), 1239\u20131252 (2005)","journal-title":"Trans. VLSI"},{"key":"3_CR28","doi-asserted-by":"publisher","DOI":"10.1002\/0470033371","volume-title":"Multi-Voltage CMOS Circuit Design","author":"V Kursun","year":"2006","unstructured":"Kursun, V., Friedman, E.G.: Multi-Voltage CMOS Circuit Design. Wiley, West Sussex (2006)"},{"issue":"2","key":"3_CR29","doi-asserted-by":"publisher","first-page":"62","DOI":"10.1109\/54.914626","volume":"18","author":"A Sinha","year":"2001","unstructured":"Sinha, A., Chandrakasan, A.P.: Dynamic power management in wireless sensor networks. IEEE Des. Test 18(2), 62\u201374 (2001)","journal-title":"IEEE Des. Test"},{"key":"3_CR30","doi-asserted-by":"crossref","unstructured":"Zarrabi, H., Al-Khalili, A.J., Savaria, Y.: An interconnect-aware delay model for dynamic voltage scaling in nm technologies. In: GLSVLSI (2009)","DOI":"10.1145\/1531542.1531557"},{"key":"3_CR31","doi-asserted-by":"crossref","unstructured":"Zarrabi, H., Al-Khalili, A.J., Savaria, Y.: Repeater design for power-managed VLSI. Submitted to GLSVLSI (2011)","DOI":"10.1145\/1973009.1973092"},{"key":"3_CR32","doi-asserted-by":"crossref","unstructured":"Zarrabi, H., Al-Khalili, A.J., Savaria, Y.: An interconnect-aware dynamic voltage scaling scheme for DSM VLSI. In: ISCAS, May 2010","DOI":"10.1109\/ISCAS.2010.5537106"},{"key":"3_CR33","doi-asserted-by":"crossref","unstructured":"Sakurai, T.: Approximation of wiring delay in MOS-FET LSI. IEEE J. Solid-State Circuits SC-18(4), 418\u2013426 (1983)","DOI":"10.1109\/JSSC.1983.1051966"},{"key":"3_CR34","volume-title":"Digital Integrated Circuits: A Design Perspective","author":"J Rabaey","year":"2003","unstructured":"Rabaey, J., Chandrakasan, A., Nikolic, B.: Digital Integrated Circuits: A Design Perspective, 2nd edn. Prentice Hall, Upper Saddle River (2003)","edition":"2"},{"issue":"1","key":"3_CR35","doi-asserted-by":"publisher","first-page":"55","DOI":"10.1063\/1.1697872","volume":"19","author":"WC Elmore","year":"1948","unstructured":"Elmore, W.C.: The transient response of damped linear networks with particular regard to wide-band amplifiers. J. Appl. Phys. 19(1), 55\u201363 (1948)","journal-title":"J. Appl. Phys."},{"issue":"11","key":"3_CR36","first-page":"1671","volume":"49","author":"J Cong","year":"2002","unstructured":"Cong, J., Pan, D.Z.: Wire width planning for interconnect performance optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits 49(11), 1671\u20131677 (2002)","journal-title":"IEEE Trans. Comput. Aided Des. Integr. Circuits"},{"key":"3_CR37","unstructured":"Zarrabi, H., Saaied, H., Al-Khalili, A.J., Savaria, Y.: Zero skew differential clock distribution network. In: International Symposium on Circuit and Systems (ISCAS), May 2006"},{"key":"3_CR38","unstructured":"Zhang, J., Friedman, E.G.: Decoupling technique and crosstalk analysis of coupled RLC interconnects. In: Proceedings of the IEEE International Symposium on Circuits and Systems II, pp. 521\u2013524 , May 2004"},{"key":"3_CR39","doi-asserted-by":"crossref","unstructured":"Kahng, A.B., Muddu, S., Sarto, E.: On switch factor based analysis of coupled RC interconnects. In: Proceedings of the Design Automation Conference, June 2000","DOI":"10.1145\/337292.337318"},{"key":"3_CR40","unstructured":"Pileggi, L.: Coping with RC(L) interconnect design headaches. IEEE ICCAD Tutorial, November 1995"},{"key":"3_CR41","unstructured":"Yee, G., Chandra, R., Ganesan, V., Sechen, C.: Wire delay in the presence of crosstalk. ACM\/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, December 1997"},{"key":"3_CR42","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-0947-3","volume-title":"On and Off-chip Cross-talk Avoidance in VLSI Designs","author":"C Duan","year":"2010","unstructured":"Duan, C., LaMeres, B.J., Khatri, S.: On and Off-chip Cross-talk Avoidance in VLSI Designs. Springer, New York (2010)"},{"key":"3_CR43","unstructured":"Zhao, W., Cao, Y.: New generation of predictive technology model for sub-45nm design exploration. IEEE International Symposium on Quality Electronic Design (ISQED) (2006)"},{"key":"3_CR44","unstructured":"International Technology Roadmap for Semiconductors: http:\/\/www.itrs.net"},{"key":"3_CR45","unstructured":"Berkeley Predictive Technology Model. http:\/\/www-device.eecs.berkeley.edu\/ptm"},{"key":"3_CR46","doi-asserted-by":"publisher","first-page":"2272","DOI":"10.1109\/TED.2005.856795","volume":"52","author":"XC Li","year":"2005","unstructured":"Li, X.C., Mao, J.F., Huang, H.F., Liu, Y.: Global interconnect width and spacing optimization for latency, bandwidth and power dissipation. IEEE Trans. Electron. Devices 52, 2272\u20132279 (2005)","journal-title":"IEEE Trans. Electron. Devices"},{"key":"3_CR47","volume-title":"Sub-Threshold Design for Ultra Low-Power Systems","author":"A Wang","year":"2006","unstructured":"Wang, A., Calhoun, B.H., Chandrakasan, A.P.: Sub-Threshold Design for Ultra Low-Power Systems. Springer, New York (2006)"},{"issue":"1","key":"3_CR48","doi-asserted-by":"publisher","first-page":"310","DOI":"10.1109\/JSSC.2004.837945","volume":"40","author":"A Wang","year":"2005","unstructured":"Wang, A., Chandrakasan, A.P.: A 180-mV subthreshold FFT processor using a minimum energy design methodology. IEEE J. Solid-State Circuits 40(1), 310\u2013319 (2005)","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"2","key":"3_CR49","doi-asserted-by":"publisher","first-page":"267","DOI":"10.1109\/JPROC.2009.2037211","volume":"98","author":"HB Calhoun","year":"2010","unstructured":"Calhoun, H.B., Ryan, J., Khanna, S., Putic, M., Lach, J.: Flexible circuits and architectures for ultra low power. Proc. IEEE 98(2), 267\u2013282 (2010)","journal-title":"Proc. IEEE"},{"issue":"2","key":"3_CR50","doi-asserted-by":"publisher","first-page":"191","DOI":"10.1109\/JPROC.2009.2033621","volume":"98","author":"AP Chandrakasan","year":"2010","unstructured":"Chandrakasan, A.P., Daly, D.C., Finchelstein, D.F., Kwong, J., Ramadass, Y.K., Sinangil, M.E., Sze, V., Verma, N.: Technologies for ultradynamic voltage scaling. Proc. IEEE 98(2), 191\u2013214 (2010)","journal-title":"Proc. IEEE"},{"key":"3_CR51","unstructured":"Forestier, A., Stan, M.R.: Limits to voltage scaling from the low power perspective. In: Symposium on Integrated Circuits and Systems Design, September 2000"},{"key":"3_CR52","doi-asserted-by":"crossref","unstructured":"Macchiarulo, L., Macii, E., Poncino, M.: Low-Energy encoding for deep-submicron address buses. In: ISLPED (2001)","DOI":"10.1145\/383082.383127"},{"key":"3_CR53","doi-asserted-by":"crossref","unstructured":"Kalyan, T.V., Mutyam, M., Rao, P.V.: Exploiting Variable Cycle Transmission for Energy-Efficient On-Chip Interconnect Design. In: International Conference on VLSI Design (2008)","DOI":"10.1109\/VLSI.2008.15"},{"key":"3_CR54","doi-asserted-by":"crossref","unstructured":"Ghoneima, M., Ismail, Y., Khellah, M.M., Tschanz, J., De, V.: Serial-link bus: a low-power on-chip bus architecture. Trans. Circuits Sys. Part I (2009)","DOI":"10.1109\/TCSI.2008.2010155"},{"key":"3_CR55","doi-asserted-by":"crossref","unstructured":"Sotiriadis,, P.P., Chandrakasan, A.P.: A bus energy model for deep submicron technology, IEEE Trans. Very Large Scale Integr. Syst., June 2002","DOI":"10.1109\/TVLSI.2002.1043337"},{"key":"3_CR56","doi-asserted-by":"crossref","unstructured":"Sotiriadis, P., Chandrakasan, A.P.: Bus Energy Reduction by Transition Pattern Coding Using a Detailed Deep Submicrometer Bus Model, IEEE Trans. Circuits Syst., pp. 1280\u20131295, October 2003","DOI":"10.1109\/TCSI.2003.817765"},{"key":"3_CR57","doi-asserted-by":"crossref","unstructured":"Deogun, H., Rao, R.M., Sylvester, D., Brown, R., Nowka, K.: Dynamically pulsed MTCMOS with bus encoding for total power and crosstalk minimization. In: IEEE International Symposium on Quality Electronic Design, pp. 88\u201393 (2005)","DOI":"10.1109\/ISQED.2005.49"},{"key":"3_CR58","unstructured":"Benini, L., De Micheli, G., Macii, E., Sciuto, D., Silvano, S.: Address bus encoding techniques for system-level power optimization, In: Proceedings of the Conference on Design, Automation and Test in Europe, February 1998"},{"key":"3_CR59","doi-asserted-by":"crossref","unstructured":"Suresh, D.C., Agrawal, B., Yang, J., Najjar, W.A.: Tunable and energy efficient bus encoding techniques, IEEE Trans. Comput. (2009)","DOI":"10.1109\/TC.2009.39"}],"container-title":["Computational Intelligence in Digital and Network Designs and Applications"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-319-20071-2_3","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,29]],"date-time":"2025-05-29T04:59:43Z","timestamp":1748494783000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-319-20071-2_3"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015]]},"ISBN":["9783319200705","9783319200712"],"references-count":59,"URL":"https:\/\/doi.org\/10.1007\/978-3-319-20071-2_3","relation":{},"subject":[],"published":{"date-parts":[[2015]]},"assertion":[{"value":"15 July 2015","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}}]}}