{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,29]],"date-time":"2025-05-29T05:40:07Z","timestamp":1748497207110,"version":"3.41.0"},"publisher-location":"Cham","reference-count":37,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783319200705"},{"type":"electronic","value":"9783319200712"}],"license":[{"start":{"date-parts":[[2015,1,1]],"date-time":"2015-01-01T00:00:00Z","timestamp":1420070400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2015,1,1]],"date-time":"2015-01-01T00:00:00Z","timestamp":1420070400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015]]},"DOI":"10.1007\/978-3-319-20071-2_7","type":"book-chapter","created":{"date-parts":[[2015,7,14]],"date-time":"2015-07-14T07:20:48Z","timestamp":1436858448000},"page":"191-221","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["Low-Power NoC Using Optimum Adaptation"],"prefix":"10.1007","author":[{"given":"Sayed T.","family":"Muhammad","sequence":"first","affiliation":[]},{"given":"Rabab","family":"Ezz-Eldin","sequence":"additional","affiliation":[]},{"given":"Magdy A.","family":"El-Moursy","sequence":"additional","affiliation":[]},{"given":"Amr M.","family":"Refaat","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2015,7,15]]},"reference":[{"key":"7_CR1","volume-title":"System-on-a-Chip Design and Test","author":"R Rajsuman","year":"2000","unstructured":"Rajsuman, R.: System-on-a-Chip Design and Test. Kluwer, Boston (2000)"},{"issue":"6","key":"7_CR2","doi-asserted-by":"publisher","first-page":"1050","DOI":"10.1109\/JPROC.2006.873611","volume":"94","author":"R Saleh","year":"2006","unstructured":"Saleh, R., Wilton, S., Mirabbasi, S., Hu, A., Greenstreet, M., Lemieux, G., Pande, P., Grecu, C., Ivanov, A.: System-on-chip: reuse and integrate. Proc. IEEE 94(6), 1050\u20131069 (2006)","journal-title":"Proc. IEEE"},{"issue":"1","key":"7_CR3","doi-asserted-by":"publisher","first-page":"70","DOI":"10.1109\/2.976921","volume":"35","author":"L Benini","year":"2002","unstructured":"Benini, L., Micheli, G.: Networks on chips: a new SoC paradigm. IEEE Comput. 35(1), 70\u201378 (2002)","journal-title":"IEEE Comput."},{"issue":"1","key":"7_CR4","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/1132952.1132953","volume":"38","author":"T Bjerregaard","year":"2006","unstructured":"Bjerregaard, T., Mahadevan, S.: A survey of research and practices of network-on-chip. Proc. ACM Comput. Surv. 38(1), 1 (2006)","journal-title":"Proc. ACM Comput. Surv."},{"issue":"5","key":"7_CR5","doi-asserted-by":"publisher","first-page":"404","DOI":"10.1109\/MDT.2005.108","volume":"22","author":"P Pande","year":"2005","unstructured":"Pande, P., Grecu, C., Ivanov, A., Saleh, R., De Micheli, G.: Design, synthesis and test of networks on chip. IEEE Des. Test Comput. 22(5), 404\u2013413 (2005)","journal-title":"IEEE Des. Test Comput."},{"key":"7_CR6","doi-asserted-by":"crossref","unstructured":"Grecu, C.: Structured interconnect archiecture: a solution for the non-scalablility of bus-based SoCs. In: The Proceedings of the Great Lakes Symposium on VLSI, pp. 192\u2013195, April 2004","DOI":"10.1145\/988952.988999"},{"issue":"1","key":"7_CR7","doi-asserted-by":"publisher","first-page":"69","DOI":"10.1016\/j.vlsi.2004.03.003","volume":"38","author":"F Moraes","year":"2004","unstructured":"Moraes, F., Calazans, N., Mello, A., M\u00f6ller, L., Ost, L.: HERMES: an infrastructure for low area overhead packet-switching networks on chip. Integr. VLSI J 38(1), 69\u201393 (2004)","journal-title":"Integr. VLSI J"},{"key":"7_CR8","doi-asserted-by":"crossref","unstructured":"Dally, W., Towles, B.: Route packets, not wires: on-chip interconnection networks: In: The IEEE Proceedings of the Design Automation Conference, pp. 684\u2013689, June 2001","DOI":"10.1145\/378239.379048"},{"key":"7_CR9","doi-asserted-by":"crossref","unstructured":"Ali, M., Welzl, M., Zwicknagl, M.: Networks on chips: scalable interconnects for future systems on chips. In: The Proceedings of the European Conference on Circuits and Systems for Communications, pp. 240\u2013245, July 2008","DOI":"10.1109\/ECCSC.2008.4611685"},{"key":"7_CR10","unstructured":"Hemani, A., Jantsch, A., Kumar, S., Postula, A., Oberg, J., Millberg, M., Lindqvist, D.: Network on a chip: an architecture for billion transistor era. In: The Proceedings of IEEE NorChip Conference, pp. 166\u2013173, November 2000"},{"key":"7_CR11","doi-asserted-by":"crossref","unstructured":"Huan, Y., DeHon, A\/: FPGA optimized packet-switched NoC using split and merge primitives. In: The Proceedings of IEEE International Conference on Field-Programmable Technology, pp. 47\u201352, December 2012","DOI":"10.1109\/FPT.2012.6412110"},{"issue":"3","key":"7_CR12","doi-asserted-by":"publisher","first-page":"340","DOI":"10.1016\/j.vlsi.2007.12.002","volume":"41","author":"D Atienza","year":"2008","unstructured":"Atienza, D., Angiolini, F., Murali, S., Pullini, A., Benini, L., Micheli, G.: Network-on-chip design and synthesis outlook. Integr. VLSI J 41(3), 340\u2013359 (2008)","journal-title":"Integr. VLSI J"},{"key":"7_CR13","doi-asserted-by":"crossref","unstructured":"Xu, Y., Jianyang, Z., Liu, S.: Research and analysis of routing algorithms for NoC. In: The Proceedings of Computer Research and Development, vol. 2, pp. 98\u2013102, May 2011","DOI":"10.1109\/ICCRD.2011.5764092"},{"key":"7_CR14","doi-asserted-by":"crossref","unstructured":"Zhang, W., Hou, L., Wang, J., Geng, S., Wu, W.: Comparison research between XY and odd-even routing algorithm of a 2-dimension 3X3 mesh topology network-on-chip. In: The Proceedings of WRI Global Congress on Intelligent Systems, vol. 3, pp. 329\u2013333 (2009)","DOI":"10.1109\/GCIS.2009.110"},{"issue":"2","key":"7_CR15","doi-asserted-by":"publisher","first-page":"194","DOI":"10.1109\/71.127260","volume":"3","author":"W Dally","year":"1992","unstructured":"Dally, W.: Virtual-channel flow control. IEEE Trans. Parallel Distrib. Syst. 3(2), 194\u2013205 (1992)","journal-title":"IEEE Trans. Parallel Distrib. Syst."},{"issue":"8","key":"7_CR16","doi-asserted-by":"publisher","first-page":"1025","DOI":"10.1109\/TC.2005.134","volume":"54","author":"P Pande","year":"2005","unstructured":"Pande, P., Grecu, C., Jones, M., Lvanov, A., Saleh, R.: Performance evaluation and design trade-offs for network-on-chip interconnect architectures. IEEE Trans. Comput. 54(8), 1025\u20131040 (2005)","journal-title":"IEEE Trans. Comput."},{"key":"7_CR17","unstructured":"Sharma, P., Bairathi, R.: Study and analysis of the behavior of a generic mesh architecture of NoC routers. In: The Proceeding of the International Multi-Conference of Engineers and Computer Scientists, vol. II, pp. 17\u201319, March 2010"},{"key":"7_CR18","first-page":"539","volume":"2010","author":"M Nadi","year":"2010","unstructured":"Nadi, M., Ghadiry, M., Dermany, M.: The effect of number of virtual channel on NOC EDP. J. Appl. Math. Inf. 2010, 539\u2013551 (2010)","journal-title":"J. Appl. Math. Inf."},{"issue":"8","key":"7_CR19","doi-asserted-by":"publisher","first-page":"869","DOI":"10.1109\/TVLSI.2007.900742","volume":"15","author":"S Murali","year":"2007","unstructured":"Murali, S., Atienza, D., Meloni, P., Carta, S., Benini, L., Micheli, G., Raffo, L.: Synthesis of predictable networks-on-chip-based interconnect architectures for chip multiprocessors. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 15(8), 869\u2013880 (2007)","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"7_CR20","doi-asserted-by":"crossref","unstructured":"Burd, T., Brodersen, R.: Energy Efficient Microprocessor Design, pp. 376. Kluwer Academic Publishers, Boston (2002)","DOI":"10.1007\/978-1-4615-0875-5"},{"issue":"12","key":"7_CR21","doi-asserted-by":"publisher","first-page":"1498","DOI":"10.1109\/43.898828","volume":"19","author":"T Kam","year":"2000","unstructured":"Kam, T., Rawat, S., Kirkpatrick, D., Roy, R., Spirakis, G., Sherwani, N., Peterson, C.: EDA challenges facing future microprocessor design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(12), 1498\u20131506 (2000)","journal-title":"IEEE Trans. Comput. Aided Des. Integr. Circuits Syst."},{"issue":"2","key":"7_CR22","doi-asserted-by":"publisher","first-page":"148","DOI":"10.1109\/TVLSI.2005.863753","volume":"14","author":"K Lee","year":"2006","unstructured":"Lee, K., Lee, S., Yoo, H.: Low-power network-on-chip for high performance SoC design. IEEE Trans. Very Large Scale Integr. Syst. (TVLSI) 14(2), 148\u2013160 (2006)","journal-title":"IEEE Trans. Very Large Scale Integr. Syst. (TVLSI)"},{"key":"7_CR23","doi-asserted-by":"crossref","unstructured":"Milojevic, D., Montperrus, L., Verkest, D.: Power dissipation of the network-on-chip in a system-on-chip for MPEG-4 video encoding. In: IEEE Transactions on Solid-State Circuits, pp. 392\u2013395, November 2007","DOI":"10.1109\/ASSCC.2007.4425713"},{"key":"7_CR24","doi-asserted-by":"crossref","unstructured":"Hu, Y., Zhu, Y., Chen, H., Graham, R., Cheng, C.: Communication latency aware low power NoC synthesis. In: The Proceedings of the IEEE\/ACM Design Automation Conference, pp. 574\u2013579 (2006)","DOI":"10.1145\/1146909.1147058"},{"key":"7_CR25","doi-asserted-by":"crossref","unstructured":"Chouchene, W., Attia, B., Zitouni, A., Abid, N., Tourki, R.: A low power network interface for network on chip. In: The Proceeding of the International Multi-Conference on Systems, Signals and Devices, pp. 1\u20136, March 2011","DOI":"10.1109\/SSD.2011.5767464"},{"issue":"2","key":"7_CR26","doi-asserted-by":"publisher","first-page":"49","DOI":"10.1109\/L-CA.2010.15","volume":"9","author":"Z Fang","year":"2010","unstructured":"Fang, Z., Hallnor, E., Li, B., Leddige, M., Dai, D.: Boomerang: reducing power consumption of response packets in NoCs with minimal performance impact. J. IEEE Comput. Archit. Lett. 9(2), 49\u201352 (2010)","journal-title":"J. IEEE Comput. Archit. Lett."},{"issue":"5","key":"7_CR27","first-page":"303","volume":"8","author":"R Ezz-Eldin","year":"2011","unstructured":"Ezz-Eldin, R., El-Moursy, M., Refaat, A.: Low power NoC switch using novel adaptive virtual channels. IJCSI Int. J. Comput. Sci. Issues 8(5), 303\u2013308 (2011)","journal-title":"IJCSI Int. J. Comput. Sci. Issues"},{"key":"7_CR28","doi-asserted-by":"crossref","unstructured":"Ezz-Eldin, R., El-Moursy, M., Refaat, A.: Novel adaptive virtual channels technique for NoC switch. In: The Proceedings of the IEEE International Design and Test Workshop, pp. 7\u201311, December 2011","DOI":"10.1109\/IDT.2011.6123093"},{"key":"7_CR29","doi-asserted-by":"crossref","unstructured":"Ezz-Eldin, R., El-Moursy, M., Refaat, A.: Low leakage power NoC switch using AVC. In: The Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2549\u20132552, May 2012","DOI":"10.1109\/ISCAS.2012.6271823"},{"key":"7_CR30","unstructured":"Wang, H., Peh, L., Malik, S.: A power for routers: modeling alpha 21364 and Infiniband routers. In: The Proceeding of the Symposium on High Performance Interconnects, pp. 21\u201327, August 2002"},{"key":"7_CR31","unstructured":"Wei, L., Roy, K., Vivek, D.: Low voltage low power CMOS design techniques for deep submicron ICs. In: The Proceedings of the International Conference on VLSI Design, pp. 24\u201329, January 2000"},{"key":"7_CR32","volume-title":"Digital Integrated Circuits","author":"J Rabaey","year":"2003","unstructured":"Rabaey, J., Chandrakasan, A., Nikolic, B.: Digital Integrated Circuits. Prentice Hall, Upper Saddle River (2003)"},{"key":"7_CR33","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-2355-0","volume-title":"Low-power digital VLSI design","author":"A Bellaouar","year":"1995","unstructured":"Bellaouar, A., Elmasry, M.: Low-power digital VLSI design. Kluwer Academic Publishers, Boston (1995)"},{"key":"7_CR34","doi-asserted-by":"crossref","unstructured":"Benini, L.: Application specific NoC design. In: The Proceedings of the Design, Automation and Test in Europe, vol. 1, pp. 1\u20135 (2006)","DOI":"10.1109\/DATE.2006.243857"},{"issue":"3","key":"7_CR35","doi-asserted-by":"publisher","first-page":"333","DOI":"10.1016\/j.micpro.2013.02.003","volume":"37","author":"B Talwar","year":"2013","unstructured":"Talwar, B., Amrutur, B.: Traffic engineered NoC for streaming applications. Microprocess. Microsyst. 37(3), 333\u2013344 (2013)","journal-title":"Microprocess. Microsyst."},{"key":"7_CR36","doi-asserted-by":"crossref","unstructured":"Muhammad, S.T., El-Moursy, M.A., El-Moursy, A.A., Refaat, A.M.: Traffic-based virtual channel activation for low-power NoC. In: The Proceedings of IEEE International Design and Test Workshop IDT, pp. 1\u20136, December 2013","DOI":"10.1109\/IDT.2013.6727077"},{"key":"7_CR37","unstructured":"Jain, L.: NIRGAM: a dynamic systemC simulator for NoC. http:\/\/nirgam.ecs.soton.ac.uk"}],"container-title":["Computational Intelligence in Digital and Network Designs and Applications"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-319-20071-2_7","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,29]],"date-time":"2025-05-29T04:59:18Z","timestamp":1748494758000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-319-20071-2_7"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015]]},"ISBN":["9783319200705","9783319200712"],"references-count":37,"URL":"https:\/\/doi.org\/10.1007\/978-3-319-20071-2_7","relation":{},"subject":[],"published":{"date-parts":[[2015]]},"assertion":[{"value":"15 July 2015","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}}]}}