{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T12:03:39Z","timestamp":1759147419835,"version":"3.40.3"},"publisher-location":"Cham","reference-count":23,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783319208596"},{"type":"electronic","value":"9783319208602"}],"license":[{"start":{"date-parts":[[2015,1,1]],"date-time":"2015-01-01T00:00:00Z","timestamp":1420070400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2015,1,1]],"date-time":"2015-01-01T00:00:00Z","timestamp":1420070400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015]]},"DOI":"10.1007\/978-3-319-20860-2_15","type":"book-chapter","created":{"date-parts":[[2015,6,19]],"date-time":"2015-06-19T08:15:57Z","timestamp":1434701757000},"page":"233-247","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":6,"title":["Towards Line-Aware Realizations of Expressions for HDL-Based Synthesis of Reversible Circuits"],"prefix":"10.1007","author":[{"given":"Zaid","family":"Al-Wardi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Robert","family":"Wille","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rolf","family":"Drechsler","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2015,6,20]]},"reference":[{"key":"15_CR1","unstructured":"Nielsen, M., Chuang, I.: Quantum Computation and Quantum Information. Cambridge Univ. Press (2000)"},{"key":"15_CR2","doi-asserted-by":"publisher","first-page":"187","DOI":"10.1038\/nature10872","volume":"483","author":"A Berut","year":"2012","unstructured":"Berut, A., Arakelyan, A., Petrosyan, A., Ciliberto, S., Dillenschneider, R., Lutz, E.: Experimental verification of Landauer\u2019s principle linking information and thermodynamics. Nature 483, 187\u2013189 (2012)","journal-title":"Nature"},{"key":"15_CR3","doi-asserted-by":"crossref","unstructured":"Wille, R., Drechsler, R., Oswald, C., Garcia-Ortiz, A.: Automatic design of low-power encoders using reversible circuit synthesis. In: Design, Automation and Test in Europe, pp. 1036\u20131041 (2012)","DOI":"10.1109\/DATE.2012.6176648"},{"key":"15_CR4","doi-asserted-by":"crossref","unstructured":"Miller, D.M., Maslov, D., Dueck, G.W.: A transformation based algorithm for reversible logic synthesis. In: Design Automation Conf., pp. 318\u2013323 (2003)","DOI":"10.1145\/775832.775915"},{"issue":"6","key":"15_CR5","doi-asserted-by":"publisher","first-page":"710","DOI":"10.1109\/TCAD.2003.811448","volume":"22","author":"VV Shende","year":"2003","unstructured":"Shende, V.V., Prasad, A.K., Markov, I.L., Hayes, J.P.: Synthesis of reversible logic circuits. IEEE Trans. on CAD 22(6), 710\u2013722 (2003)","journal-title":"IEEE Trans. on CAD"},{"key":"15_CR6","doi-asserted-by":"crossref","unstructured":"Wille, R., Le, H.M., Dueck, G.W., Gro\u00dfe, D.: Quantified synthesis of reversible logic. In: Design, Automation and Test in Europe, pp. 1015\u20131020 (2008)","DOI":"10.1145\/1403375.1403620"},{"key":"15_CR7","doi-asserted-by":"crossref","unstructured":"Wille, R., Drechsler, R.: BDD-based synthesis of reversible logic for large functions. In: Design Automation Conf., pp. 270\u2013275 (2009)","DOI":"10.1145\/1629911.1629984"},{"key":"15_CR8","doi-asserted-by":"crossref","unstructured":"Soeken, M., Wille, R., Hilken, C., Przigoda, N., Drechsler, R.: Synthesis of reversible circuits with minimal lines for large functions. In: ASP Design Automation Conf., pp. 85\u201392 (2012)","DOI":"10.1109\/ASPDAC.2012.6165069"},{"key":"15_CR9","doi-asserted-by":"crossref","unstructured":"Feinstein, D.Y., Thornton, M.A., Miller, D.M.: Partially redundant logic detection using symbolic equivalence checking in reversible and irreversible logic circuits. In: Design, Automation and Test in Europe, pp. 1378\u20131381 (2008)","DOI":"10.1145\/1403375.1403707"},{"key":"15_CR10","doi-asserted-by":"crossref","unstructured":"Soeken, M., Wille, R., Dueck, G.W., Drechsler, R.: Window optimization of reversible and quantum circuits. In: IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (2010)","DOI":"10.1109\/DDECS.2010.5491754"},{"key":"15_CR11","doi-asserted-by":"crossref","unstructured":"Viamontes, G.F., Markov, I.L., Hayes, J.P.: Checking equivalence of quantum circuits and states. In: Int\u2019l Conf. on CAD, pp. 69\u201374 (2007)","DOI":"10.1109\/ICCAD.2007.4397246"},{"issue":"2","key":"15_CR12","doi-asserted-by":"publisher","first-page":"584","DOI":"10.1093\/ietfec\/e91-a.2.584","volume":"91\u2013A","author":"SA Wang","year":"2008","unstructured":"Wang, S.A., Lu, C.Y., Tsai, I.M., Kuo, S.Y.: An XQDD-based verification method for quantum circuits. IEICE Transactions 91\u2013A(2), 584\u2013594 (2008)","journal-title":"IEICE Transactions"},{"key":"15_CR13","doi-asserted-by":"crossref","unstructured":"Wille, R., Gro\u00dfe, D., Frehse, S., Dueck, G.W., Drechsler, R.: Debugging of toffoli networks. In: Design, Automation and Test in Europe, pp. 1284\u20131289 (2009)","DOI":"10.1109\/DATE.2009.5090863"},{"key":"15_CR14","doi-asserted-by":"crossref","unstructured":"Polian, I., Fiehn, T., Becker, B., Hayes, J.P.: A family of logical fault models for reversible circuits. In: Asian Test Symp., pp. 422\u2013427 (2005)","DOI":"10.1109\/ATS.2005.9"},{"key":"15_CR15","doi-asserted-by":"crossref","unstructured":"Wille, R., Zhang, H., Drechsler, R.: ATPG for reversible circuits using simulation, boolean satisfiability, and pseudo boolean optimization. In: IEEE Annual Symposium on VLSI, pp. 120\u2013125 (2011)","DOI":"10.1109\/ISVLSI.2011.77"},{"key":"15_CR16","doi-asserted-by":"crossref","unstructured":"Wille, R., Offermann, S., Drechsler, R.: SyReC: A programming language forsynthesis of reversible circuits. In: Forum on Specification and Design Languages. pp. 184\u2013189. Springer, Heidelberg (2010)","DOI":"10.1049\/ic.2010.0150"},{"key":"15_CR17","doi-asserted-by":"crossref","unstructured":"Wille, R., Soeken, M., Gro\u00dfe, D., Sch\u00f6nborn, E., Drechsler, R.: Designing a RISC CPU in reversible logic. In: Int\u2019l Symp. on Multi-Valued Logic, pp. 170\u2013175 (2011)","DOI":"10.1109\/ISMVL.2011.39"},{"key":"15_CR18","doi-asserted-by":"crossref","unstructured":"Wille, R., Soeken, M., Sch\u00f6nborn, E., Drechsler, R.: Circuit line minimization in the HDL-based synthesis of reversible logic. In: IEEE Annual Symposium on VLSI, pp. 213\u2013218 (2012)","DOI":"10.1109\/ISVLSI.2012.43"},{"issue":"11","key":"15_CR19","doi-asserted-by":"publisher","first-page":"1497","DOI":"10.1109\/TCAD.2004.836735","volume":"23","author":"D Maslov","year":"2004","unstructured":"Maslov, D., Dueck, G.W.: Reversible cascades with minimal garbage. IEEE Trans. on CAD 23(11), 1497\u20131509 (2004)","journal-title":"IEEE Trans. on CAD"},{"key":"15_CR20","doi-asserted-by":"crossref","unstructured":"Wille, R., Kesz\u00f6cze, O., Drechsler, R.: Determining the minimal number of lines for large reversible circuits. In: Design, Automation and Test in Europe, pp. 1204\u20131207 (2011)","DOI":"10.1109\/DATE.2011.5763314"},{"key":"15_CR21","doi-asserted-by":"crossref","unstructured":"Yokoyama, T., Gl\u00fcck, R.: A reversible programming language and its invertible self-interpreter. In: Symp. on Partial Evaluation and Semantics-Based Program Manipulation, pp. 144\u2013153 (2007)","DOI":"10.1145\/1244381.1244404"},{"key":"15_CR22","doi-asserted-by":"crossref","unstructured":"Wille, R., Gro\u00dfe, D., Teuber, L., Dueck, G.W., Drechsler, R.: RevLib: an online resource for reversible functions and reversible circuits. In: Int\u2019l Symp. on Multi-Valued Logic, pp. 220\u2013225 (2008). RevLib is available at http:\/\/www.revlib.org","DOI":"10.1109\/ISMVL.2008.43"},{"issue":"2","key":"15_CR23","doi-asserted-by":"publisher","first-page":"284","DOI":"10.1016\/j.vlsi.2013.08.002","volume":"47","author":"R Wille","year":"2014","unstructured":"Wille, R., Soeken, M., Miller, D.M., Drechsler, R.: Trading off circuit lines and gate costs in the synthesis of reversible logic. INTEGRATION, the VLSI Jour. 47(2), 284\u2013294 (2014)","journal-title":"INTEGRATION, the VLSI Jour."}],"container-title":["Lecture Notes in Computer Science","Reversible Computation"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-319-20860-2_15","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,2,8]],"date-time":"2023-02-08T12:59:35Z","timestamp":1675861175000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-319-20860-2_15"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015]]},"ISBN":["9783319208596","9783319208602"],"references-count":23,"URL":"https:\/\/doi.org\/10.1007\/978-3-319-20860-2_15","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2015]]},"assertion":[{"value":"20 June 2015","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}}]}}