{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,16]],"date-time":"2025-07-16T13:31:13Z","timestamp":1752672673592},"publisher-location":"Cham","reference-count":18,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783319264066"},{"type":"electronic","value":"9783319264080"}],"license":[{"start":{"date-parts":[[2016,1,1]],"date-time":"2016-01-01T00:00:00Z","timestamp":1451606400000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016]]},"DOI":"10.1007\/978-3-319-26408-0_1","type":"book-chapter","created":{"date-parts":[[2016,6,17]],"date-time":"2016-06-17T02:32:11Z","timestamp":1466130731000},"page":"1-21","source":"Crossref","is-referenced-by-count":6,"title":["FPGA Versus Software Programming: Why, When, and How?"],"prefix":"10.1007","author":[{"given":"Dirk","family":"Koch","sequence":"first","affiliation":[]},{"given":"Daniel","family":"Ziener","sequence":"additional","affiliation":[]},{"given":"Frank","family":"Hannig","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2016,6,18]]},"reference":[{"key":"1_CR36","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4020-6100-4","volume-title":"Introduction to Reconfigurable Computing: Architectures, Algorithms, and Applications","author":"C. Bobda","year":"2007","unstructured":"C.\u00a0Bobda. Introduction to Reconfigurable Computing: Architectures, Algorithms, and Applications. Springer, 2007."},{"key":"1_CR40","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4615-5145-4","volume-title":"Architecture and CAD for Deep-Submicron FPGAs","author":"V. Betz","year":"1999","unstructured":"V.\u00a0Betz, J.\u00a0Rose, and A.\u00a0Marquardt. Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic Publishers, 1999."},{"issue":"1","key":"1_CR56","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1109\/43.273754","volume":"13","author":"J. Cong","year":"1994","unstructured":"J.\u00a0Cong and Y.\u00a0Ding. FlowMap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 13(1):1\u201312, Jan 1994.","journal-title":"Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on"},{"key":"1_CR77","doi-asserted-by":"crossref","unstructured":"R.\u00a0H. Dennard, F.\u00a0H. Gaensslen, H.\u00a0nien Yu, V.\u00a0L. Rideout, E.\u00a0Bassous, Andre, and R.\u00a0Leblanc. Design of ion-implanted MOSFETs with very small physical dimensions. IEEE J. Solid-State Circuits, 87(4):668\u2013678, 1974.","DOI":"10.1109\/JPROC.1999.752522"},{"key":"1_CR88","doi-asserted-by":"crossref","unstructured":"R.\u00a0J. Francis, J.\u00a0Rose, and K.\u00a0Chung. Chortle: A technology mapping program for lookup table-based field programmable gate arrays. In Proceedings of the 27th ACM\/IEEE Design Automation Conference, DAC \u201990, pages 613\u2013619, New York, NY, USA, 1990. ACM.","DOI":"10.1145\/123186.123418"},{"key":"1_CR98","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4615-3636-9","volume-title":"High-level Synthesis: Introduction to Chip and System Design","author":"D. D. Gajski","year":"1992","unstructured":"D.\u00a0D. Gajski, N.\u00a0D. Dutt, A.\u00a0C.-H. Wu, and S.\u00a0Y.-L. Lin. High-level Synthesis: Introduction to Chip and System Design. Kluwer Academic Publishers, Norwell, MA, USA, 1992."},{"issue":"2","key":"1_CR103","doi-asserted-by":"crossref","first-page":"86","DOI":"10.1109\/MM.2011.18","volume":"31","author":"N. Goulding-Hotta","year":"2011","unstructured":"N.\u00a0Goulding-Hotta, J.\u00a0Sampson, G.\u00a0Venkatesh, S.\u00a0Garcia, J.\u00a0Auricchio, P.\u00a0Huang, M.\u00a0Arora, S.\u00a0Nath, V.\u00a0Bhatt, J.\u00a0Babb, S.\u00a0Swanson, and M.\u00a0Taylor. The GreenDroid mobile application processor: An architecture for silicon\u2019s dark future. IEEE Micro, 31(2):86\u201395, March\u2013April 2011.","journal-title":"IEEE Micro"},{"key":"1_CR113","volume-title":"Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation","author":"S. Hauck","year":"2007","unstructured":"S.\u00a0Hauck and A.\u00a0DeHon. Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation. Morgan Kaufmann Publishers Inc., San Francisco, CA, USA, 2007."},{"key":"1_CR139","doi-asserted-by":"crossref","unstructured":"D.\u00a0Koch, C.\u00a0Beckhoff, and J.\u00a0Teich. ReCoBus-Builder: A novel tool and technique to build statically and dynamically reconfigurable systems for FPGAs. In Field Programmable Logic and Applications, FPL 2008. International Conference on, pages 119 \u2013124, sept. 2008.","DOI":"10.1109\/FPL.2008.4629918"},{"key":"1_CR142","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4614-1225-0","volume-title":"Partial Reconfiguration on FPGAs \u2013 Architectures, Tools and Applications","author":"D. Koch","year":"2013","unstructured":"D.\u00a0Koch. Partial Reconfiguration on FPGAs \u2013 Architectures, Tools and Applications. Springer, 2013."},{"key":"1_CR144","doi-asserted-by":"crossref","unstructured":"I.\u00a0Kuon and J.\u00a0Rose. Measuring the gap between FPGAs and ASICs. In Proceedings of the 2006 ACM\/SIGDA 14th International Symposium on Field Programmable Gate Arrays, (FPGA) \u201906, pages 21\u201330, New York, NY, USA, 2006. ACM.","DOI":"10.1145\/1117201.1117205"},{"key":"1_CR157","doi-asserted-by":"crossref","unstructured":"L.\u00a0Mcmurchie and C.\u00a0Ebeling. Pathfinder: A negotiation-based performance-driven router for FPGAs. In Proceedings of the 1995 ACM third International Symposium on Field-Programmable Gate Arrays (FPGA), pages 111\u2013117, 1995.","DOI":"10.1145\/201310.201328"},{"issue":"8","key":"1_CR162","first-page":"114","volume":"38","author":"G. Moore","year":"1965","unstructured":"G.\u00a0Moore. Cramming more components onto integrated circuits. Electronics, 38(8):114\u2013117, April 1965.","journal-title":"Electronics"},{"key":"1_CR187","doi-asserted-by":"crossref","unstructured":"A.\u00a0Putnam, A.\u00a0M. Caulfield, E.\u00a0S. Chung, D.\u00a0Chiou, K.\u00a0Constantinides, J.\u00a0Demme, H.\u00a0Esmaeilzadeh, J.\u00a0Fowers, G.\u00a0P. Gopal, J.\u00a0Gray, M.\u00a0Haselman, S.\u00a0Hauck, S.\u00a0Heil, A.\u00a0Hormati, J.-Y. Kim, S.\u00a0Lanka, J.\u00a0Larus, E.\u00a0Peterson, S.\u00a0Pope, A.\u00a0Smith, J.\u00a0Thong, P.\u00a0Y. Xiao, and D.\u00a0Burger. A reconfigurable fabric for accelerating large-scale datacenter service. In Proceedings of the ACM\/IEEE 41st International Symposium on Computer Architecture (ISCA), pages 13\u201324. IEEE, 2014.","DOI":"10.1109\/ISCA.2014.6853195"},{"key":"1_CR195","doi-asserted-by":"crossref","unstructured":"A.\u00a0Rodchenko, A.\u00a0Nisbet, A.\u00a0Pop, and M.\u00a0Lujan. Effective barrier synchronization on Intel Xeon Phi coprocessor. In 20th International Conference on Parallel Processing (Euro-Par), (Springer 2015), pp. 588\u2013600.","DOI":"10.1007\/978-3-662-48096-0_45"},{"key":"1_CR197","doi-asserted-by":"crossref","unstructured":"J.\u00a0Robinson, S.\u00a0Vafaee, J.\u00a0Scobbie, M.\u00a0Ritche, and J.\u00a0Rose. The supersmall soft processor, in VI Southern Programmable Logic Conference (SPL) (2010), pp 3\u20138.","DOI":"10.1109\/SPL.2010.5483016"},{"key":"1_CR224","doi-asserted-by":"crossref","unstructured":"E.\u00a0Vermij, L.\u00a0Fiorin, C.\u00a0Hagleitner, and K.\u00a0Bertels. Exascale radio astronomy: Can we ride the technology wave? In J.\u00a0Kunkel, T.\u00a0Ludwig, and H.\u00a0Meuer, editors, Supercomputing, volume 8488 of Lecture Notes in Computer Science, pages 35\u201352. Springer International Publishing, 2014.","DOI":"10.1007\/978-3-319-07518-1_3"},{"key":"1_CR252","doi-asserted-by":"crossref","unstructured":"M.\u00a0Yue, D.\u00a0Koch, and G.\u00a0Lemieux. Rapid overlay builder for xilinx FPGAs. In Field-Programmable Custom Computing Machines (FCCM), 2015 IEEE 23rd Annual International Symposium on, pages 17\u201320, May 2015.","DOI":"10.1109\/FCCM.2015.48"}],"container-title":["FPGAs for Software Programmers"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-319-26408-0_1","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,9]],"date-time":"2019-09-09T17:33:00Z","timestamp":1568050380000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-319-26408-0_1"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016]]},"ISBN":["9783319264066","9783319264080"],"references-count":18,"URL":"https:\/\/doi.org\/10.1007\/978-3-319-26408-0_1","relation":{},"subject":[],"published":{"date-parts":[[2016]]}}}