{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,1]],"date-time":"2025-06-01T04:10:45Z","timestamp":1748751045713,"version":"3.41.0"},"publisher-location":"Cham","reference-count":25,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783319271187"},{"type":"electronic","value":"9783319271194"}],"license":[{"start":{"date-parts":[[2015,1,1]],"date-time":"2015-01-01T00:00:00Z","timestamp":1420070400000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015]]},"DOI":"10.1007\/978-3-319-27119-4_7","type":"book-chapter","created":{"date-parts":[[2015,11,16]],"date-time":"2015-11-16T04:39:29Z","timestamp":1447648769000},"page":"91-102","source":"Crossref","is-referenced-by-count":2,"title":["Memory-Aware NoC Application Mapping Based on Adaptive Genetic Algorithm"],"prefix":"10.1007","author":[{"given":"Yizhuo","family":"Wang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhibiao","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lifu","family":"Huang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Weixing","family":"Ji","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2015,12,16]]},"reference":[{"key":"7_CR1","doi-asserted-by":"publisher","first-page":"70","DOI":"10.1109\/2.976921","volume":"35","author":"L Benini","year":"2002","unstructured":"Benini, L., De Micheli, G.: Networks on chips: a new SoC paradigm. IEEE Comput. 35, 70\u201378 (2002)","journal-title":"IEEE Comput."},{"key":"7_CR2","doi-asserted-by":"crossref","unstructured":"Dally, W.J., Towles, B.: Route packets, not wires: on-chip interconnection networks. In: Proceedings of the 38th Design Automation Conference (DAC), pp. 684\u2013689 (2001)","DOI":"10.1145\/378239.379048"},{"key":"7_CR3","doi-asserted-by":"crossref","unstructured":"Kumar, S., Jantsch, A., Soininen, J. P., Forsell, M., Millberg, M., Oberg, J, Tiensyrja, K., Hemani, A.: A network on chip architecture and design methodology. In: Proceedings of ISVLSI, pp. 117\u2013124 (2002)","DOI":"10.1109\/ISVLSI.2002.1016885"},{"key":"7_CR4","unstructured":"Pop, R., Kumar, S.: A survey of techniques for mapping and scheduling applications to network on chip systems. Research Report, J\u00f6nk\u00f6ping University (2004)"},{"key":"7_CR5","doi-asserted-by":"crossref","unstructured":"Wang, X., Gan, G., Manzano, J., Fan, D., Guo, S.: A quantitative study of the on-chip network and memory hierarchy design for many core processor. In: Proceedings of ICPADS (2008)","DOI":"10.1109\/ICPADS.2008.18"},{"key":"7_CR6","doi-asserted-by":"crossref","unstructured":"Yoo, J., Yoo, S., Choi, K.: Multiprocessor system-on-chip designs with active memory processors for higher memory efficiency. In: Proceedings of DAC (2009)","DOI":"10.1145\/1629911.1630118"},{"issue":"7","key":"7_CR7","doi-asserted-by":"publisher","first-page":"233","DOI":"10.1016\/j.sysarc.2010.03.001","volume":"56","author":"S Lee","year":"2010","unstructured":"Lee, S., Yoon, Y., Hwang, S.: Communication-aware task assignment algorithm for MPSoC using shared memory. J. Syst. Architect. 56(7), 233\u2013241 (2010)","journal-title":"J. Syst. Architect."},{"key":"7_CR8","doi-asserted-by":"crossref","unstructured":"Lee, J., Choi, K.: Memory-aware mapping and scheduling of tasks and communications on many-core SoC. In: ASP-DAC, pp. 419\u2013424 (2012)","DOI":"10.1109\/ASPDAC.2012.6164985"},{"key":"7_CR9","doi-asserted-by":"crossref","unstructured":"Zhou, W., Zhang, Y., Mao, Z.: An application specific NoC mapping for optimized delay. In: IEEE International Conference on Design and Test of Integrated Systems in Nanoscale, DTIS, vol. 45, no. 2, pp. 184\u2013188 (2006)","DOI":"10.1109\/DTIS.2006.1708657"},{"key":"7_CR10","doi-asserted-by":"crossref","unstructured":"Cheng, X., Yang, C.: Robot path planning based on adaptive isolation niche genetic algorithm. In: Proceedings of 2nd International Symposium on Intelligent Information Technology Application, pp. 151\u2013154 (2008)","DOI":"10.1109\/IITA.2008.130"},{"key":"7_CR11","doi-asserted-by":"crossref","unstructured":"Chen, G., Li, F., Kandemir, M.: Compiler-directed application mapping for NoC based chip multiprocessors. In: Proceedings of LCTES, pp. 155\u2013157 (2007)","DOI":"10.1145\/1273444.1254796"},{"issue":"10","key":"7_CR12","doi-asserted-by":"publisher","first-page":"1866","DOI":"10.1109\/TCAD.2008.2003301","volume":"27","author":"CL Chou","year":"2008","unstructured":"Chou, C.L., Ogras, U.Y., Marculescu, R.: Energy- and performance-aware incremental mapping for NoCs with multiple voltage levels. IEEE Trans. Comput. Aided Des. Integr. Circ. Syst. 27(10), 1866\u20131879 (2008)","journal-title":"IEEE Trans. Comput. Aided Des. Integr. Circ. Syst."},{"key":"7_CR13","doi-asserted-by":"crossref","unstructured":"Carvalho, E., Moraes, F.: Congestion-aware task mapping in heterogeneous MPSoCs. In: International Symposium on SoC, pp. 1\u20134 (2008)","DOI":"10.1109\/ISSOC.2008.4694878"},{"key":"7_CR14","doi-asserted-by":"crossref","unstructured":"Ostler, C., Chatha, K.S.: An ILP formulation for system-level application mapping on network processor architecture. In: Proceedings of Design, Automation and Test in Europe (DATE), pp. 1\u20136 (2007)","DOI":"10.1109\/DATE.2007.364574"},{"key":"7_CR15","doi-asserted-by":"crossref","unstructured":"Hu, J. Marculescu, R.: Energy-aware mapping for tile-based NoC architectures under performance constraints. In: Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 233\u2013239 (2003)","DOI":"10.1145\/1119772.1119818"},{"key":"7_CR16","doi-asserted-by":"crossref","unstructured":"Kennedy, I., Eberhart, R.C.: Particle swarm optimization. In: Proceedings of IEEE International Conference on Neural Networks, NJ, pp. 1942\u20131948(1995)","DOI":"10.1109\/ICNN.1995.488968"},{"key":"7_CR17","unstructured":"Colorni, A., Dorigo, M., Maniezzo, V.: Distributed optimization by ant colonies. In: Actes de la Premi\u00e8re Conf\u00e9rence Europ\u00e9enne sur la vie Artificielle. Elsevier Publishing, Paris, France (1991)"},{"key":"7_CR18","doi-asserted-by":"crossref","unstructured":"Harmanani, H.M., Farah, R.: A method for efficient mapping and reliable routing for NoC architectures with minimum bandwidth and area. In: IEEE International Workshop on Circuits and systems and TAISA Conference (NEWCAS-TAISA), pp. 29\u201332 (2008)","DOI":"10.1109\/NEWCAS.2008.4606313"},{"key":"7_CR19","doi-asserted-by":"crossref","unstructured":"Lei, T., Kumar, S.: A two-step genetic algorithm for mapping task graphs to a network on chip architecture. In: Proceedings of the Euromicro Symposium on Digital System Design (DSD), vol. 17, no. 35, pp. 180\u2013187 (2003)","DOI":"10.1109\/DSD.2003.1231923"},{"key":"7_CR20","doi-asserted-by":"crossref","unstructured":"Ascia, G., Catania, V., Palesi, M.: Multi-objective mapping for mesh-based NoC architectures. In: ACM International Conference on Hardware\/Software Codesign and System Synthesis, vol 42, no. 12, pp. 182\u2013187 (2004)","DOI":"10.1145\/1016720.1016765"},{"key":"7_CR21","doi-asserted-by":"crossref","unstructured":"Jena, R.K., Sharma, G.K.: A multi-objective evolutionary algorithm based optimization model for Network-on-Chip synthesis. In: IEEE International Conference on Information Technology (ITNG), vol. 21, no. 4, pp. 977\u2013982 (2007)","DOI":"10.1109\/ITNG.2007.10"},{"issue":"11","key":"7_CR22","doi-asserted-by":"publisher","first-page":"795","DOI":"10.1016\/j.sysarc.2007.01.013","volume":"53","author":"H Orsila","year":"2007","unstructured":"Orsila, H., Kangas, T., Salminen, E., Hamalainen, T., Hannikainen, M.: Automated memory-aware application distribution for multi-processor system-on-chips. J. Syst. Architect. 53(11), 795\u2013815 (2007)","journal-title":"J. Syst. Architect."},{"issue":"7","key":"7_CR23","doi-asserted-by":"publisher","first-page":"233","DOI":"10.1016\/j.sysarc.2010.03.001","volume":"56","author":"S Lee","year":"2010","unstructured":"Lee, S., Yoon, Y., Hwang, S.: Communication-aware task assignment algorithm for MPSoC using shared memory. J. Syst. Architect. 56(7), 233\u2013241 (2010)","journal-title":"J. Syst. Architect."},{"issue":"4","key":"7_CR24","first-page":"656","volume":"24","author":"M Srinivas","year":"1994","unstructured":"Srinivas, M.: PATNAILKLM: Adaptive probabilities of crossover and mutation in genetic algorithms. IEEE Trans. Syst. 24(4), 656\u2013667 (1994)","journal-title":"IEEE Trans. Syst."},{"key":"7_CR25","doi-asserted-by":"crossref","unstructured":"Dick, R., Rhodes, D., Wolf, W.: TGFF: task graphs for free: hardware\/software codesign. In: Proceedings of the Hardware\/Software Codesign, Seattle, USA (1998)","DOI":"10.1145\/278241.278309"}],"container-title":["Lecture Notes in Computer Science","Algorithms and Architectures for Parallel Processing"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-319-27119-4_7","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,31]],"date-time":"2025-05-31T11:59:33Z","timestamp":1748692773000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-319-27119-4_7"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015]]},"ISBN":["9783319271187","9783319271194"],"references-count":25,"URL":"https:\/\/doi.org\/10.1007\/978-3-319-27119-4_7","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2015]]}}}