{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,1]],"date-time":"2025-06-01T19:40:09Z","timestamp":1748806809708,"version":"3.41.0"},"publisher-location":"Cham","reference-count":12,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783319304809"},{"type":"electronic","value":"9783319304816"}],"license":[{"start":{"date-parts":[[2016,1,1]],"date-time":"2016-01-01T00:00:00Z","timestamp":1451606400000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016]]},"DOI":"10.1007\/978-3-319-30481-6_24","type":"book-chapter","created":{"date-parts":[[2016,3,12]],"date-time":"2016-03-12T08:09:38Z","timestamp":1457770178000},"page":"303-311","source":"Crossref","is-referenced-by-count":0,"title":["Fast and Resource Aware Image Processing Operators Utilizing Highly Configurable IP Blocks"],"prefix":"10.1007","author":[{"given":"Konrad","family":"H\u00e4ublein","sequence":"first","affiliation":[]},{"given":"Christian","family":"Hartmann","sequence":"additional","affiliation":[]},{"given":"Marc","family":"Reichenbach","sequence":"additional","affiliation":[]},{"given":"Dietmar","family":"Fey","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2016,3,13]]},"reference":[{"key":"24_CR1","unstructured":"Altera: Implementing FPGA Design with the OpenCL Standard - White Paper, November 2013. https:\/\/www.altera.com\/en_US\/pdfs\/literature\/wp\/wp-01173-opencl.pdf"},{"key":"24_CR2","unstructured":"Altera: Video and Image Processing Suite, February 2014. www.altera.co.jp\/ja_JP\/pdfs\/literature\/ug\/ug_vip.pdf"},{"key":"24_CR3","doi-asserted-by":"crossref","DOI":"10.1002\/9780470828519","volume-title":"Design for Embedded Image Processing on FPGAs","author":"DG Bailey","year":"2011","unstructured":"Bailey, D.G.: Design for Embedded Image Processing on FPGAs. Wiley-IEEE Press, Singapore (2011)"},{"issue":"6","key":"24_CR4","doi-asserted-by":"crossref","first-page":"679","DOI":"10.1109\/TPAMI.1986.4767851","volume":"PAMI-8","author":"John Canny","year":"1986","unstructured":"Canny, J.: A Computational approach to edge detection. In: Pattern Analysis and Machine Intelligence, pp. 679\u2013698, November 1986","journal-title":"IEEE Transactions on Pattern Analysis and Machine Intelligence"},{"key":"24_CR5","unstructured":"Hartman, C., Reichenbach, M., Fey, D.: Ipol - a Domain specific language for image processing applications. In: Proceedings of the International Symposium on International Conference on Systems (ICONS), pp. 40\u201343, March 2015"},{"key":"24_CR6","doi-asserted-by":"crossref","unstructured":"H\u00e4ublein, K., Reichenbach, M., Fey, D.: Fast and generic hardware architecture for stereo block matching applications on embedded systems. In: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), pp. 1\u20136, December 2014","DOI":"10.1109\/ReConFig.2014.7032518"},{"key":"24_CR7","doi-asserted-by":"crossref","unstructured":"Reiche, O., Schmidt, M., Hannig, F., Membarth, R., Teich, J.: Code generation from a domain-specific language for C-based HLS of hardware accelerators. In: Proceedings of the 2014 International Conference on Hardware\/Software Codesign and System Synthesis, pp. 1\u201310, October 2014","DOI":"10.1145\/2656075.2656081"},{"key":"24_CR8","doi-asserted-by":"crossref","unstructured":"Scharstein, D., Szeliski, R.: High-accuracy stereo depth maps using structured light. In: IEEE Computer Society Conference on Computer Vision and Pattern Recognition (CVpPR 2003), pp. 195\u2013202, June 2003","DOI":"10.1109\/CVPR.2003.1211354"},{"key":"24_CR9","doi-asserted-by":"crossref","unstructured":"Schmidt, M., Reichenbach, M., Fey, D.: A generic VHDL template for 2D stencil code applications on FPGAs. In: 15th International Symposium on Object\/Component\/Service-Oriented Real-Time Distributed Computing Workshops, pp. 180\u2013187, April 2012","DOI":"10.1109\/ISORCW.2012.39"},{"key":"24_CR10","unstructured":"Xilinx: Image Enhancement v8.0: LogiCORE IP Product Guide, October 2014. http:\/\/www.xilinx.com\/support\/documentation\/ip_documentation\/v_enhance\/v8_0\/pg003_v_enhance.pdf"},{"key":"24_CR11","unstructured":"Xilinx: Vivado Design Suite User Guide: High-Level Synthesis, October 2014. http:\/\/www.xilinx.com\/support\/documentation\/sw_manuals\/xilinx2014_3\/ug902-vivado-high-level-synthesis.pdf"},{"key":"24_CR12","unstructured":"Xilinx: Accelerating OpenCV Applications with Zynq-7000 All Programmable SoC using Vivado HLS Video Libraries, June 2015. http:\/\/www.xilinx.com\/support\/documentation\/application_notes\/xapp1167.pdf"}],"container-title":["Lecture Notes in Computer Science","Applied Reconfigurable Computing"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-319-30481-6_24","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,1]],"date-time":"2025-06-01T19:20:55Z","timestamp":1748805655000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-319-30481-6_24"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016]]},"ISBN":["9783319304809","9783319304816"],"references-count":12,"URL":"https:\/\/doi.org\/10.1007\/978-3-319-30481-6_24","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2016]]}}}