{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,1]],"date-time":"2025-06-01T19:40:09Z","timestamp":1748806809485,"version":"3.41.0"},"publisher-location":"Cham","reference-count":10,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783319304809"},{"type":"electronic","value":"9783319304816"}],"license":[{"start":{"date-parts":[[2016,1,1]],"date-time":"2016-01-01T00:00:00Z","timestamp":1451606400000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016]]},"DOI":"10.1007\/978-3-319-30481-6_25","type":"book-chapter","created":{"date-parts":[[2016,3,12]],"date-time":"2016-03-12T08:09:38Z","timestamp":1457770178000},"page":"312-319","source":"Crossref","is-referenced-by-count":1,"title":["Performance Evaluation of Feed-Forward Backpropagation Neural Network for Classification on a Reconfigurable Hardware Architecture"],"prefix":"10.1007","author":[{"given":"Mahnaz","family":"Mohammadi","sequence":"first","affiliation":[]},{"given":"Rohit","family":"Ronge","sequence":"additional","affiliation":[]},{"given":"Sanjay S.","family":"Singapuram","sequence":"additional","affiliation":[]},{"given":"S. K.","family":"Nandy","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2016,3,13]]},"reference":[{"key":"25_CR1","doi-asserted-by":"crossref","unstructured":"Cloutier, J., Simard, P.Y.: Hardware implementation of the backpropagation without multiplication. In: Proceedings of the Fourth International Conference on Microelectronics for Neural Networks and Fuzzy Systems, pp. 46\u201355. IEEE (1994)","DOI":"10.1109\/ICMNN.1994.593174"},{"key":"25_CR2","doi-asserted-by":"crossref","unstructured":"Domingos, P.O., Silva, F.M., Neto, H.C.: An efficient and scalable architecture for neural networks with backpropagation learning. In: International Conference on Field Programmable Logic and Applications, pp. 89\u201394. IEEE (2005)","DOI":"10.1109\/FPL.2005.1515704"},{"key":"25_CR3","doi-asserted-by":"crossref","unstructured":"Eldredge, J.G., Hutchings, B.L.: Rrann: a hardware implementation of the backpropagation algorithm using reconfigurable fpgas. In: IEEE International Conference on Neural Networks, IEEE World Congress on Computational Intelligence, vol. 4, pp. 2097\u20132102 (1994)","DOI":"10.1109\/ICNN.1994.374538"},{"key":"25_CR4","doi-asserted-by":"crossref","unstructured":"Madhu, K.T., Das, S., Madhava Krishna, C., Nalesh, S., Nandy, S.K., Narayan, R.: Synthesis of instruction extensions on hypercell, a reconfigurable datapath. In: International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), pp. 215\u2013224. IEEE (2014)","DOI":"10.1109\/SAMOS.2014.6893214"},{"key":"25_CR5","doi-asserted-by":"crossref","unstructured":"Mahoney, V., Elhanany, I.: A backpropagation neural network design using adder-only arithmetic. In: 51st Midwest Symposium on Circuits and Systems, MWSCAS, pp. 894\u2013897. IEEE (2008)","DOI":"10.1109\/MWSCAS.2008.4616944"},{"key":"25_CR6","doi-asserted-by":"crossref","unstructured":"Mohammadi, M., et al.: An accelerator for classification using radial basis function neural network. In: 28th IEEE International System-On-Chip Conference (SOCC) (2015)","DOI":"10.1109\/SOCC.2015.7406928"},{"key":"25_CR7","doi-asserted-by":"crossref","unstructured":"Mohammadi, M., et al.: A flexible scalable hardware architecture for radial basis function neural networks. In: 28th International Conference on VLSI Design, pp. 505\u2013510. IEEE (2015)","DOI":"10.1109\/VLSID.2015.91"},{"key":"25_CR8","doi-asserted-by":"crossref","unstructured":"Ortega-Zamorano, F., et al.: Efficient implementation of the backpropagation algorithm in fpgas and microcontrollers. IEEE Trans. Neural Netw. Learn. Syst.(2015)","DOI":"10.1109\/TNNLS.2015.2460991"},{"key":"25_CR9","doi-asserted-by":"crossref","unstructured":"Kimball Presley, R., Haggard, R.L.: A fixed point implementation of the backpropagation learning algorithm. In: Southeastcon 1994. Creative Technology Transfer-A Global Affair, Proceedings of the IEEE, pp. 136\u2013138 (1994)","DOI":"10.1109\/SECON.1994.324283"},{"key":"25_CR10","doi-asserted-by":"crossref","unstructured":"Rajeswaran, N., Madhu, T., Suryakalavathi, M.: Vhdl synthesizable hardware architecture design of back propagation neural networks. In: IEEE Conference on Information and Communication Technologies (ICT), pp. 445\u2013450 (2013)","DOI":"10.1109\/CICT.2013.6558137"}],"container-title":["Lecture Notes in Computer Science","Applied Reconfigurable Computing"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-319-30481-6_25","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,1]],"date-time":"2025-06-01T19:20:51Z","timestamp":1748805651000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-319-30481-6_25"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016]]},"ISBN":["9783319304809","9783319304816"],"references-count":10,"URL":"https:\/\/doi.org\/10.1007\/978-3-319-30481-6_25","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2016]]}}}