{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,9]],"date-time":"2024-09-09T03:09:45Z","timestamp":1725851385674},"publisher-location":"Cham","reference-count":11,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783319304809"},{"type":"electronic","value":"9783319304816"}],"license":[{"start":{"date-parts":[[2016,1,1]],"date-time":"2016-01-01T00:00:00Z","timestamp":1451606400000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016]]},"DOI":"10.1007\/978-3-319-30481-6_30","type":"book-chapter","created":{"date-parts":[[2016,3,12]],"date-time":"2016-03-12T08:09:38Z","timestamp":1457770178000},"page":"352-360","source":"Crossref","is-referenced-by-count":0,"title":["Adaptive Bandwidth Router for 3D Network-on-Chips"],"prefix":"10.1007","author":[{"given":"Stephanie","family":"Friederich","sequence":"first","affiliation":[]},{"given":"Niclas","family":"Lehmann","sequence":"additional","affiliation":[]},{"given":"J\u00fcrgen","family":"Becker","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2016,3,13]]},"reference":[{"issue":"5","key":"30_CR1","doi-asserted-by":"publisher","first-page":"602","DOI":"10.1109\/5.929647","volume":"89","author":"K Banerjee","year":"2001","unstructured":"Banerjee, K., Souri, S.J., Kapur, P., Saraswat, K.C.: 3-D ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration. Proc. IEEE 89(5), 602\u2013633 (2001)","journal-title":"Proc. IEEE"},{"key":"30_CR2","unstructured":"Bell, S., Edwards, B., Amann, J., Conlin, R., Joyce, K., Leung, V., MacKay, J., Reif, M., Bao, L., Brown, J., et al.: TILE64-processor: a 64-core SoC with mesh interconnect. In: IEEE International Solid-State Circuits Conference on Digest of Technical Papers, 2008, ISSCC 2008, pp. 88\u2013598. IEEE (2008)"},{"key":"30_CR3","unstructured":"Committee, I.R., et al.: International technology roadmap for semiconductors, 2011 edn. Semiconductor Industry Association (2011). http:\/\/www.itrs.net\/ITRS"},{"key":"30_CR4","unstructured":"Hei\u00dfwolf, J.: A Scalable and Adaptive Network on Chip for Many-Core Architectures. Ph.D. thesis, Karlsruhe, Karlsruher Institut f\u00fcr Technologie (KIT), Diss., 2014 (2014)"},{"key":"30_CR5","unstructured":"Heisswolf, J., Zaib, A., Weichslgartner, A., Karle, M., Singh, M., Wild, T., Teich, J., Herkersdorf, A., Becker, J.: The invasive network on chip - a multi-objective many-core communication infrastructure. In: 2014 27th International Conference on Architecture of Computing Systems (ARCS), pp. 1\u20138. VDE (2014)"},{"key":"30_CR6","doi-asserted-by":"crossref","unstructured":"Liu, C., Zhang, L., Han, Y., Li, X.: Vertical interconnects squeezing in symmetric 3D mesh network-on-chip. In: Proceedings of the 16th Asia and South Pacific Design Automation Conference, pp. 357\u2013362. IEEE Press (2011)","DOI":"10.1109\/ASPDAC.2011.5722213"},{"issue":"6","key":"30_CR7","doi-asserted-by":"publisher","first-page":"1214","DOI":"10.1109\/JPROC.2006.873612","volume":"94","author":"RS Patti","year":"2006","unstructured":"Patti, R.S.: Three-dimensional integrated circuits and the future of system-on-chip designs. Proc. IEEE 94(6), 1214\u20131224 (2006)","journal-title":"Proc. IEEE"},{"issue":"10","key":"30_CR8","doi-asserted-by":"publisher","first-page":"1081","DOI":"10.1109\/TVLSI.2007.893649","volume":"15","author":"VF Pavlidis","year":"2007","unstructured":"Pavlidis, V.F., Friedma, E.G.: 3-D topologies for networks-on-chip. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 15(10), 1081\u20131090 (2007)","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"issue":"4.5","key":"30_CR9","doi-asserted-by":"publisher","first-page":"491","DOI":"10.1147\/rd.504.0491","volume":"50","author":"AW Topol","year":"2006","unstructured":"Topol, A.W., La Tulipe, D., Shi, L., Frank, D.J., Bernstein, K., Steen, S.E., Kumar, A., Singco, G.U., Young, A.M., Guarini, K.W., et al.: Three-dimensional integrated circuits. IBM J. Res. Dev. 50(4.5), 491\u2013506 (2006)","journal-title":"IBM J. Res. Dev."},{"issue":"1","key":"30_CR10","doi-asserted-by":"publisher","first-page":"73","DOI":"10.1145\/1945023.1945033","volume":"45","author":"RF Wijngaart Van der","year":"2011","unstructured":"Van der Wijngaart, R.F., Mattson, T.G., Haas, W.: Light-weight communications on intel\u2019s single-chip cloud computer processor. ACM SIGOPS Operating Syst. Rev. 45(1), 73\u201383 (2011)","journal-title":"ACM SIGOPS Operating Syst. Rev."},{"key":"30_CR11","doi-asserted-by":"crossref","unstructured":"Xu, T.C., Liljeberg, P., Tenhunen, H.: Optimal number and placement of through silicon vias in 3D network-on-chip. In: 2011 IEEE 14th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), pp. 105\u2013110. IEEE (2011)","DOI":"10.1109\/DDECS.2011.5783057"}],"container-title":["Lecture Notes in Computer Science","Applied Reconfigurable Computing"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-319-30481-6_30","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,5]],"date-time":"2019-09-05T13:45:01Z","timestamp":1567691101000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-319-30481-6_30"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016]]},"ISBN":["9783319304809","9783319304816"],"references-count":11,"URL":"https:\/\/doi.org\/10.1007\/978-3-319-30481-6_30","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2016]]}}}