{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,11]],"date-time":"2025-06-11T04:10:51Z","timestamp":1749615051812,"version":"3.41.0"},"publisher-location":"Cham","reference-count":25,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783319454795"},{"type":"electronic","value":"9783319454801"}],"license":[{"start":{"date-parts":[[2016,1,1]],"date-time":"2016-01-01T00:00:00Z","timestamp":1451606400000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016]]},"DOI":"10.1007\/978-3-319-45480-1_12","type":"book-chapter","created":{"date-parts":[[2016,9,2]],"date-time":"2016-09-02T15:08:20Z","timestamp":1472828900000},"page":"144-156","source":"Crossref","is-referenced-by-count":1,"title":["Gate-Level-Accurate Fault-Effect Analysis at Virtual-Prototype Speed"],"prefix":"10.1007","author":[{"given":"Bogdan-Andrei","family":"Tabacaru","sequence":"first","affiliation":[]},{"given":"Moomen","family":"Chaari","sequence":"additional","affiliation":[]},{"given":"Wolfgang","family":"Ecker","sequence":"additional","affiliation":[]},{"given":"Thomas","family":"Kruse","sequence":"additional","affiliation":[]},{"given":"Cristiano","family":"Novello","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2016,9,1]]},"reference":[{"key":"12_CR1","unstructured":"ISO, CD. 26262, Road Vehicles-Functional Safety. International Standard ISO\/FDIS, 26262 (2011)"},{"key":"12_CR2","unstructured":"Open SystemC Initiative et al.: IEEE Standard SystemC Language Reference Manual. IEEE Computer Society (2006)"},{"key":"12_CR3","doi-asserted-by":"crossref","unstructured":"Oetjens, J.-H., Bringmann, O., Chaari, M., Ecker, W., Tabacaru, B.-A., et al.: Safetyevaluation of automotive electronics using virtual prototypes: state of the art and research challenges. In: 51st ACM\/EDAC\/IEEE Design Automation Conference (DAC), pp. 1\u20136. IEEE (2014)","DOI":"10.1145\/2593069.2602976"},{"key":"12_CR4","doi-asserted-by":"crossref","first-page":"784","DOI":"10.1007\/s11432-011-4366-9","volume":"54","author":"R Baranowski","year":"2011","unstructured":"Baranowski, R., Hatami, N., Kochte, M.A., Prinetto, P., et al.: Efficient multi-level fault simulation of HW\/SW systems for structural faults. Sci. Chin. Inf. Sci. 54, 784\u20131796 (2011)","journal-title":"Sci. Chin. Inf. Sci."},{"key":"12_CR5","doi-asserted-by":"crossref","unstructured":"Tabacaru, B.-A., Chaari, M., Ecker, W., Kruse, T., Novello, C.: Fault-effect analysis on multiple abstraction levels in hardware modeling. In: DVCon, USA, pp. 1\u201312 (2016)","DOI":"10.1109\/FDL.2016.7880368"},{"key":"12_CR6","doi-asserted-by":"crossref","unstructured":"Amyeen, M.E., Nayak, D., Venkataraman, S.: Improving precision using mixed-level fault diagnosis In: IEEE International Test Conference, ITC 2006, pp. 1\u201310. IEEE (2006)","DOI":"10.1109\/TEST.2006.297661"},{"key":"12_CR7","doi-asserted-by":"crossref","unstructured":"Espinosa, J., Hernandez, C., Abella, J.: Characterizing fault propagation in safety-critical processor designs. In: IEEE 21st International On-Line Testing Symposium (IOLTS), pp. 144\u2013149. IEEE (2015)","DOI":"10.1109\/IOLTS.2015.7229848"},{"key":"12_CR8","unstructured":"STMicroelectronics: 32-bit Power Architecture Microcontroller for Automotive SIL3\/ASIL-D Chassis and Safety Applications. SPC56 Datasheet. Rev 11 (2014)"},{"key":"12_CR9","unstructured":"Infineon Technologies, A.G.: AURIX-TriCore Datasheet. Accessed 22 Feb 2016"},{"key":"12_CR10","doi-asserted-by":"crossref","unstructured":"Leveugle, R., Cimonnet, D., Ammari, A.: System-level dependability analysis with RT-level fault injection accuracy. In: Proceedings of the 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2004, pp. 451\u2013458. IEEE (2004)","DOI":"10.1109\/DFTVS.2004.1347870"},{"key":"12_CR11","unstructured":"Schwarz, M., Chaari, M., Tabacaru, B.-A., Ecker, W.: A meta model based approach for semantic fault modeling on multiple abstraction levels. In: DVCon, Europe (2015)"},{"key":"12_CR12","unstructured":"Vidrascu, I.-D.: Implementation of a safety verification environment (SVE) based on fault injection. Master\u2019s thesis, Fachhochschule K\u00e4rnten, Klagenfurt am W\u00f6rthersee, Austria (2015)"},{"key":"12_CR13","doi-asserted-by":"crossref","unstructured":"Zarandi, H.R., Miremadi, S.G., Ejlali, A.: Dependability analysis using a fault injection tool based on synthesizability of HDL models. In: Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 485\u2013492. IEEE (2003)","DOI":"10.1109\/DFTVS.2003.1250147"},{"key":"12_CR14","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"crossref","first-page":"308","DOI":"10.1007\/978-3-319-19249-9_20","volume-title":"FM 2015: Formal Methods","author":"G Brat","year":"2015","unstructured":"Brat, G., Bushnell, D., Davies, M., Giannakopoulou, D., Howar, F., Kahsai, T.: Verifying the safety of a flight-critical system. In: Bj\u00f8rner, N., Boer, F. (eds.) FM 2015. LNCS, vol. 9109, pp. 308\u2013324. Springer, Heidelberg (2015)"},{"key":"12_CR15","doi-asserted-by":"crossref","unstructured":"Sharma, V.C., Haran, A., Rakamaric, Z., Gopalakrishnan, G.: Towards formal approaches to system resilience. In: IEEE 19th Pacific Rim International Symposium on Dependable Computing (PRDC), pp. 41\u201350. IEEE (2013)","DOI":"10.1109\/PRDC.2013.14"},{"key":"12_CR16","unstructured":"Brinkmann, R.: OneSpin CEO cites 8 \u201cinsufficiencies\" in Jim Hogan\u2019s Formal Guide. Accessed 8 Mar 2016"},{"key":"12_CR17","unstructured":"Busch, H.: An automated formal verification flow for safety registers. In: DVCon, Europe (2015)"},{"key":"12_CR18","volume-title":"FPGAs and Parallel Architectures for Aerospace Applications: Soft Errors and Fault-Tolerant Design","author":"F Kastensmidt","year":"2015","unstructured":"Kastensmidt, F., Rech, P.: FPGAs and Parallel Architectures for Aerospace Applications: Soft Errors and Fault-Tolerant Design. Springer, New York (2015)"},{"issue":"2","key":"12_CR19","doi-asserted-by":"crossref","first-page":"373","DOI":"10.1007\/s11390-015-1530-5","volume":"30","author":"C Bernardeschi","year":"2015","unstructured":"Bernardeschi, C., Cassano, L., Domenici, A.: SRAM-based FPGA systems for safety-critical applications: a survey on design standards and proposed methodologies. J. Comput. Sci. Technol. 30(2), 373\u2013390 (2015)","journal-title":"J. Comput. Sci. Technol."},{"key":"12_CR20","doi-asserted-by":"crossref","unstructured":"Fang, B., Pattabiraman, K., Ripeanu, M., Gurumurthi, S.: GPU-Qin: a methodology for evaluating the error resilience of GPGPU applications. In: 2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pp. 221\u2013230. IEEE (2014)","DOI":"10.1109\/ISPASS.2014.6844486"},{"key":"12_CR21","doi-asserted-by":"crossref","unstructured":"Chang, K.-J., Chen, Y.-Y.: System-level fault injection in SystemC design platform. In: Proceedings of 8th International Symposium on Advanced Intelligent Systems (ISIS). Citeseer (2007)","DOI":"10.1109\/SSIRI.2008.11"},{"key":"12_CR22","doi-asserted-by":"crossref","unstructured":"Kochte, M., Zoellin, C.G., Baranowski, R., Imhof, M.E., Wunderlich, H.-J., Hatami, N., et al.: Efficient simulation of structural faults for the reliability evaluation at system-level. In: 2010 19th IEEE Asian Test Symposium (ATS), pp. 3\u20138. IEEE (2010)","DOI":"10.1109\/ATS.2010.10"},{"key":"12_CR23","doi-asserted-by":"crossref","unstructured":"Santos, M.B., Teixeira, J.P.: Defect-oriented mixed-level fault simulation of digital systems-on-a-chip using HDL. In: Proceedings of the Design, Automation and Test in Europe Conference and Exhibition. IEEE (1999)","DOI":"10.1109\/DATE.1999.761181"},{"key":"12_CR24","doi-asserted-by":"crossref","unstructured":"Cho, H., Mirkhani, S., Cher, C.-Y., Abraham, J.A., Mitra, S.: Quantitative evaluation of soft error injection techniques for robust system design. In: 50th ACM\/EDAC\/IEEE Design Automation Conference (DAC), pp. 1\u201310. IEEE (2013)","DOI":"10.1145\/2463209.2488859"},{"issue":"6","key":"12_CR25","doi-asserted-by":"crossref","first-page":"3278","DOI":"10.1109\/TNS.2004.839172","volume":"51","author":"PE Dodd","year":"2004","unstructured":"Dodd, P.E., Shaneyfelt, M.R., Felix, J.A., Schwank, J.R.: Production and propagation of single-event transients in high-speed digital logic ICs. IEEE Trans. Nucl. Sci. 51(6), 3278\u20133284 (2004)","journal-title":"IEEE Trans. Nucl. Sci."}],"container-title":["Lecture Notes in Computer Science","Computer Safety, Reliability, and Security"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-319-45480-1_12","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,10]],"date-time":"2025-06-10T16:20:59Z","timestamp":1749572459000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-319-45480-1_12"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016]]},"ISBN":["9783319454795","9783319454801"],"references-count":25,"URL":"https:\/\/doi.org\/10.1007\/978-3-319-45480-1_12","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2016]]}}}