{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,26]],"date-time":"2025-03-26T12:10:32Z","timestamp":1742991032932,"version":"3.40.3"},"publisher-location":"Cham","reference-count":27,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783319489889"},{"type":"electronic","value":"9783319489896"}],"license":[{"start":{"date-parts":[[2016,1,1]],"date-time":"2016-01-01T00:00:00Z","timestamp":1451606400000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016]]},"DOI":"10.1007\/978-3-319-48989-6_30","type":"book-chapter","created":{"date-parts":[[2016,11,7]],"date-time":"2016-11-07T01:31:19Z","timestamp":1478482279000},"page":"496-512","source":"Crossref","is-referenced-by-count":3,"title":["SpecCert: Specifying and Verifying Hardware-Based Security Enforcement"],"prefix":"10.1007","author":[{"given":"Thomas","family":"Letan","sequence":"first","affiliation":[]},{"given":"Pierre","family":"Chifflier","sequence":"additional","affiliation":[]},{"given":"Guillaume","family":"Hiet","sequence":"additional","affiliation":[]},{"given":"Pierre","family":"N\u00e9ron","sequence":"additional","affiliation":[]},{"given":"Benjamin","family":"Morin","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2016,11,8]]},"reference":[{"key":"30_CR1","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"231","DOI":"10.1007\/978-3-642-21437-0_19","volume-title":"FM 2011: Formal Methods","author":"G Barthe","year":"2011","unstructured":"Barthe, G., Betarte, G., Campo, J.D., Luna, C.: Formally verifying isolation and availability in an idealized model of virtualization. In: Butler, M., Schulte, W. (eds.) FM 2011. LNCS, vol. 6664, pp. 231\u2013245. Springer, Heidelberg (2011). doi: 10.1007\/978-3-642-21437-0_19"},{"key":"30_CR2","doi-asserted-by":"crossref","unstructured":"Barthe, G., Betarte, G., Campo, J.D., Luna, C.: Cache-leakage resilient OS isolation in an idealized model of virtualization. In: 2012 IEEE 25th Computer Security Foundations Symposium (CSF), pp. 186\u2013197. IEEE (2012)","DOI":"10.1109\/CSF.2012.17"},{"key":"30_CR3","doi-asserted-by":"crossref","unstructured":"Barthe, G., Betarte, G., Campo, J.D., Luna, C., Pichardie, D.: System-level non-interference for constant-time cryptography. In: Proceedings of the 2014 ACM SIGSAC Conference on Computer and Communications Security, pp. 1267\u20131279. ACM (2014)","DOI":"10.1145\/2660267.2660283"},{"issue":"1","key":"30_CR4","doi-asserted-by":"crossref","first-page":"3","DOI":"10.1145\/2487222.2487225","volume":"16","author":"D Basin","year":"2013","unstructured":"Basin, D., Jug\u00e9, V., Klaedtke, F., Z\u0103linescu, E.: Enforceable security policies revisited. ACM Trans. Inf. Syst. Secur. (TISSEC) 16(1), 3 (2013)","journal-title":"ACM Trans. Inf. Syst. Secur. (TISSEC)"},{"key":"30_CR5","unstructured":"Kallenberg, C., Cornwell, S., Kovah, X., Butterworth, J.: Setup for failure: defeating secure boot. In: The Symposium on Security for Asia Network (SyScan) (April 2014)"},{"key":"30_CR6","unstructured":"Domas, C.: The memory sinkhole. In: BlackHat USA, July 2015"},{"key":"30_CR7","doi-asserted-by":"crossref","unstructured":"Drzevitzky, S.: Proof-carrying hardware: runtime formal verification for secure dynamic reconfiguration. In: 2010 International Conference on Field Programmable Logic and Applications (FPL), pp. 255\u2013258. IEEE (2010)","DOI":"10.1109\/FPL.2010.59"},{"key":"30_CR8","doi-asserted-by":"crossref","unstructured":"Guo, X., Dutta, R.G., Mishra, P., Jin, Y.: Scalable SoC trust verification using integrated theorem proving and model checking. In: IEEE Symposium on Hardware Oriented Security and Trust, pp. 124\u2013129 (2016)","DOI":"10.1109\/HST.2016.7495569"},{"key":"30_CR9","unstructured":"Intel: CHIPSEC: Platform Security Assessment Framework. http:\/\/github.com\/chipsec\/chipsec"},{"key":"30_CR10","unstructured":"Intel: Desktop 4th Generation Intel Core Processor Family, Desktop Intel Pentium Processor Family, and Desktop Intel Celeron Processor Family"},{"key":"30_CR11","unstructured":"Intel: Intel 5100 Memory Controller Hub Chipset"},{"key":"30_CR12","unstructured":"Intel: Intel 64 and IA32 Architectures Software Developer Manual"},{"key":"30_CR13","unstructured":"Intel: Intel Trusted Execution Technology (Intel TXT), July 2015"},{"key":"30_CR14","unstructured":"Kallenberg, C., Wojtczuk, R.: Speed racer: exploiting an Intel flash protection race condition, 6 January 2015"},{"key":"30_CR15","doi-asserted-by":"crossref","unstructured":"Kennedy, A., Benton, N., Jensen, J.B., Dagand, P.E.: Coq: the world\u2019s best macro assembler? In: Proceedings of the 15th Symposium on Principles and Practice of Declarative Programming, pp. 13\u201324. ACM (2013)","DOI":"10.1145\/2505879.2505897"},{"key":"30_CR16","unstructured":"Letan, T., Hiet, G., Chifflier, P., N\u00e9ron, P., Morin, B.: SpecCert: specifying and verifying hardware-based security enforcement. Technical report, CentraleSup\u00e9lec; Agence Nationale de S\u00e9curit\u00e9 des Syst\u00e8mes d\u2019Information (2016). https:\/\/hal.inria.fr\/hal-01356690"},{"key":"30_CR17","doi-asserted-by":"crossref","unstructured":"Lie, D., Mitchell, J., Thekkath, C., Horowitz, M., et al.: Specifying and verifying hardware for tamper-resistant software. In: Proceedings of 2003 Symposium on Security and Privacy, 2003, pp. 166\u2013177. IEEE (2003)","DOI":"10.1109\/SECPRI.2003.1199335"},{"key":"30_CR18","unstructured":"Duflot, L., Levillain, O., Morin, B., Grumelard, O.: Getting into the SMRAM: SMM reloaded CanSecWest (March 2009)"},{"issue":"1","key":"30_CR19","doi-asserted-by":"crossref","first-page":"25","DOI":"10.1109\/TIFS.2011.2160627","volume":"7","author":"E Love","year":"2012","unstructured":"Love, E., Jin, Y., Makris, Y.: Proof-carrying hardware intellectual property: a pathway to trusted module acquisition. IEEE Trans. Inf. Forensics Secur. 7(1), 25\u201340 (2012)","journal-title":"IEEE Trans. Inf. Forensics Secur."},{"key":"30_CR20","unstructured":"Makris, Y.: Trusted module acquisition through proof-carrying hardware intellectual property. Technical report (2015)"},{"key":"30_CR21","doi-asserted-by":"crossref","first-page":"395","DOI":"10.1145\/2345156.2254111","volume":"47","author":"G Morrisett","year":"2012","unstructured":"Morrisett, G., Tan, G., Tassarotti, J., Tristan, J.B., Gan, E.: Rocksalt: better, faster, stronger SFI for the x86. ACM SIGPLAN Not. 47, 395\u2013404 (2012). ACM","journal-title":"ACM SIGPLAN Not."},{"key":"30_CR22","unstructured":"Wojtczuk, R., Rutkowska, J.: Attacking intel TXT via SINIT code execution hijacking. In: Black Hat DC Conference (February 2009)"},{"key":"30_CR23","unstructured":"Wojtczuk, R., Rutkowska, J.: Attacking SMM memory via intel CPU cache poisoning (March 2009)"},{"key":"30_CR24","unstructured":"Rutkowska, J., Wojtczuk, R.: Preventing and detecting Xen hypervisor subversions. In: Blackhat Briefings USA (2008)"},{"issue":"1","key":"30_CR25","doi-asserted-by":"crossref","first-page":"30","DOI":"10.1145\/353323.353382","volume":"3","author":"FB Schneider","year":"2000","unstructured":"Schneider, F.B.: Enforceable security policies. ACM Trans. Inf. Syst. Secur. (TISSEC) 3(1), 30\u201350 (2000)","journal-title":"ACM Trans. Inf. Syst. Secur. (TISSEC)"},{"issue":"7","key":"30_CR26","doi-asserted-by":"crossref","first-page":"89","DOI":"10.1145\/1785414.1785443","volume":"53","author":"P Sewell","year":"2010","unstructured":"Sewell, P., Sarkar, S., Owens, S., Nardelli, F.Z., Myreen, M.O.: x86-tso: a rigorous and usable programmer\u2019s model for x86 multiprocessors. Commun. ACM 53(7), 89\u201397 (2010)","journal-title":"Commun. ACM"},{"key":"30_CR27","unstructured":"Bulygin, Y., Loucaides, J., Furtak, A., Bazhaniuk, O., Matrosov, A.: Summary of Attacks Against BIOS and Secure Boot, def Con 22 (August 2014)"}],"container-title":["Lecture Notes in Computer Science","FM 2016: Formal Methods"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-319-48989-6_30","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,24]],"date-time":"2017-06-24T22:58:55Z","timestamp":1498345135000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-319-48989-6_30"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016]]},"ISBN":["9783319489889","9783319489896"],"references-count":27,"URL":"https:\/\/doi.org\/10.1007\/978-3-319-48989-6_30","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2016]]}}}