{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,9]],"date-time":"2024-09-09T11:28:17Z","timestamp":1725881297911},"publisher-location":"Cham","reference-count":16,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783319549989"},{"type":"electronic","value":"9783319549996"}],"license":[{"start":{"date-parts":[[2017,1,1]],"date-time":"2017-01-01T00:00:00Z","timestamp":1483228800000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017]]},"DOI":"10.1007\/978-3-319-54999-6_13","type":"book-chapter","created":{"date-parts":[[2017,3,3]],"date-time":"2017-03-03T09:51:59Z","timestamp":1488534719000},"page":"164-176","source":"Crossref","is-referenced-by-count":1,"title":["PLSS: A Scheduler for Multi-core Embedded Systems"],"prefix":"10.1007","author":[{"given":"Solomon","family":"Abera","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Balakrishnan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Anshul","family":"Kumar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2017,3,4]]},"reference":[{"key":"13_CR1","doi-asserted-by":"crossref","unstructured":"Chandra, D., Guo, F., Kim, S. and Solihin, Y.: Predicting inter-thread cache contention on a chip multi-processor architecture. In: HPCA (2005)","DOI":"10.1109\/HPCA.2005.27"},{"key":"13_CR2","doi-asserted-by":"crossref","unstructured":"Zhuravlev, S., Blagodurov, S., Fedorova, A.: Addressing shared resource contention in multicore processors via scheduling. In: ASPLOS (2010)","DOI":"10.1145\/1736020.1736036"},{"key":"13_CR3","doi-asserted-by":"crossref","unstructured":"Feliu, J. Petit, S., Sahuquillo, J., Duato, J.: Cache-hierarchy contention aware scheduling in CMPS. In: TPDS (2013)","DOI":"10.1109\/TPDS.2013.61"},{"key":"13_CR4","unstructured":"Zhang, X., Dwarkadas, S., Folkmanis, G., Shen, K.: Processor hardware counter statistics as a first-class system resource. In: HotOS (2007)"},{"key":"13_CR5","doi-asserted-by":"crossref","unstructured":"Calandrino, J.M., Anderson, J.H.: Cache-aware real-time scheduling on multicore platforms: heuristics and a case study. In: ECRTS (2008)","DOI":"10.1109\/ECRTS.2008.10"},{"key":"13_CR6","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"201","DOI":"10.1007\/978-3-642-11515-8_16","volume-title":"High Performance Embedded Architectures and Compilers","author":"Y Jiang","year":"2010","unstructured":"Jiang, Y., Tian, K., Shen, X.: Combining locality analysis with online proactive job co-scheduling in chip multiprocessors. In: Patt, Y.N., Foglia, P., Duesterwald, E., Faraboschi, P., Martorell, X. (eds.) HiPEAC 2010. LNCS, vol. 5952, pp. 201\u2013215. Springer, Heidelberg (2010). doi: 10.1007\/978-3-642-11515-8_16"},{"key":"13_CR7","doi-asserted-by":"crossref","unstructured":"Sembrant, A., Black-Schaffer, D., Hagersten, E.: Phase behavior in serial and parallel applications. In: IISWC (2012)","DOI":"10.1109\/IISWC.2012.6402900"},{"key":"13_CR8","doi-asserted-by":"crossref","unstructured":"Sherwood, T., Perlman, E., Calder, B.: Basic block distribution analysis to find periodic behavior and simulation points in applications. In: PACT (2001)","DOI":"10.1109\/PACT.2001.953283"},{"key":"13_CR9","doi-asserted-by":"crossref","unstructured":"Sherwood, T., Sair, S., Calder, B.: Phase tracking and prediction. In: ISCA (2003)","DOI":"10.1145\/859618.859657"},{"key":"13_CR10","doi-asserted-by":"crossref","unstructured":"Dhodapkar, A.S., Smith, J.E.: Managing multi-configuration hardware via dynamic working set analysis. In: ISCA (2002)","DOI":"10.1109\/ISCA.2002.1003581"},{"key":"13_CR11","doi-asserted-by":"crossref","unstructured":"Mattson, R.L., Gecsei, J., Slutz, D., Traiger. I.: Evaluation techniques for storage hierarchies (1970)","DOI":"10.1147\/sj.92.0078"},{"key":"13_CR12","doi-asserted-by":"crossref","unstructured":"Banikazemi, M., Poff, D., Abali, B.: PAM: a novel performance\/power aware meta-scheduler for multi-core systems. In: SC (2008)","DOI":"10.1109\/SC.2008.5222643"},{"key":"13_CR13","unstructured":"Freescale MPC8640D. http:\/\/www.nxp.com\/files\/32bit\/doc\/data_sheet\/MPC8640DEC.pdf"},{"key":"13_CR14","unstructured":"Broadcom. http:\/\/www.broadcom.com\/products\/Enterprise-Networking\/Communications-Processors\/BCM1255"},{"key":"13_CR15","unstructured":"ARM11MPCore. https:\/\/www.arm.com\/products\/processors\/classic\/arm11\/arm11-mpcore.php"},{"key":"13_CR16","unstructured":"Sniper Multicore Simulator. http:\/\/snipersim.org"}],"container-title":["Lecture Notes in Computer Science","Architecture of Computing Systems - ARCS 2017"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-319-54999-6_13","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,19]],"date-time":"2019-09-19T08:08:17Z","timestamp":1568880497000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-319-54999-6_13"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017]]},"ISBN":["9783319549989","9783319549996"],"references-count":16,"URL":"https:\/\/doi.org\/10.1007\/978-3-319-54999-6_13","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2017]]}}}