{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,9]],"date-time":"2024-09-09T18:27:55Z","timestamp":1725906475851},"publisher-location":"Cham","reference-count":32,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783319646466"},{"type":"electronic","value":"9783319646473"}],"license":[{"start":{"date-parts":[[2017,1,1]],"date-time":"2017-01-01T00:00:00Z","timestamp":1483228800000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017]]},"DOI":"10.1007\/978-3-319-64647-3_6","type":"book-chapter","created":{"date-parts":[[2017,7,28]],"date-time":"2017-07-28T15:33:27Z","timestamp":1501256007000},"page":"83-101","source":"Crossref","is-referenced-by-count":3,"title":["SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA"],"prefix":"10.1007","author":[{"given":"Maik","family":"Ender","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alexander","family":"Wild","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Amir","family":"Moradi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2017,7,29]]},"reference":[{"unstructured":"Side-channel attack user reference architecture. \nhttp:\/\/satoh.cs.uec.ac.jp\/SAKURA\/index.html","key":"6_CR1"},{"unstructured":"Berkeley logic synthesis, verification group, ABC: a system for sequential synthesis and verification, release ae0be2deffef. \nhttp:\/\/www.eecs.berkeley.edu\/alanmi\/abc\/","key":"6_CR2"},{"issue":"3","key":"6_CR3","doi-asserted-by":"crossref","first-page":"16","DOI":"10.1145\/2629552","volume":"8","author":"S Bhasin","year":"2015","unstructured":"Bhasin, S., Danger, J., Guilley, S., He, W.: Exploiting FPGA block memories for protected cryptographic implementations. TRETS 8(3), 16 (2015)","journal-title":"TRETS"},{"doi-asserted-by":"crossref","unstructured":"Bhasin, S., Guilley, S., Flament, F., Selmane, N., Danger, J.: Countering early evaluation: an approach towards robust dual-rail precharge logic. In: WESS 2010, p. 6. ACM (2010)","key":"6_CR4","DOI":"10.1145\/1873548.1873554"},{"key":"6_CR5","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"16","DOI":"10.1007\/978-3-540-28632-5_2","volume-title":"Cryptographic Hardware and Embedded Systems - CHES 2004","author":"E Brier","year":"2004","unstructured":"Brier, E., Clavier, C., Olivier, F.: Correlation power analysis with a leakage model. In: Joye, M., Quisquater, J.-J. (eds.) CHES 2004. LNCS, vol. 3156, pp. 16\u201329. Springer, Heidelberg (2004). doi:\n10.1007\/978-3-540-28632-5_2"},{"key":"6_CR6","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"441","DOI":"10.1007\/11545262_32","volume-title":"Cryptographic Hardware and Embedded Systems \u2013 CHES 2005","author":"D Canright","year":"2005","unstructured":"Canright, D.: A very compact S-box for AES. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, vol. 3659, pp. 441\u2013455. Springer, Heidelberg (2005). doi:\n10.1007\/11545262_32"},{"key":"6_CR7","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"242","DOI":"10.1007\/11894063_20","volume-title":"Cryptographic Hardware and Embedded Systems - CHES 2006","author":"Z Chen","year":"2006","unstructured":"Chen, Z., Zhou, Y.: Dual-rail random switching logic: a countermeasure to reduce side channel leakage. In: Goubin, L., Matsui, M. (eds.) CHES 2006. LNCS, vol. 4249, pp. 242\u2013254. Springer, Heidelberg (2006). doi:\n10.1007\/11894063_20"},{"doi-asserted-by":"crossref","unstructured":"He, W., de la Torre, E., Riesgo, T.: A precharge-absorbed DPL logic for reducing early propagation effects on FPGA implementations. In: ReConFig 2011, pp. 217\u2013222. IEEE Computer Society (2011)","key":"6_CR8","DOI":"10.1109\/ReConFig.2011.3"},{"doi-asserted-by":"crossref","unstructured":"He, W., Otero, A., de la Torre, E., Riesgo, T.: Automatic generation of identical routing pairs for FPGA implemented DPL logic. In: ReConFig 2012, pp. 1\u20136. IEEE Computer Society (2012)","key":"6_CR9","DOI":"10.1109\/ReConFig.2012.6416733"},{"doi-asserted-by":"crossref","unstructured":"Kaps, J., Velegalati, R.: DPA resistant AES on FPGA using partial DDL. In: FCCM 2010, pp. 273\u2013280. IEEE Computer Society (2010)","key":"6_CR10","DOI":"10.1109\/FCCM.2010.49"},{"doi-asserted-by":"crossref","unstructured":"Lomn\u00e9, V., Maurine, P., Torres, L., Robert, M., Soares, R., Calazans, N.: Evaluation on FPGA of triple rail logic robustness against DPA and DEMA. In: DATE 2009, pp. 634\u2013639. IEEE Computer Society (2009)","key":"6_CR11","DOI":"10.1109\/DATE.2009.5090744"},{"key":"6_CR12","volume-title":"Power Analysis Attacks: Revealing the Secrets of Smart Cards","author":"S Mangard","year":"2007","unstructured":"Mangard, S., Oswald, E., Popp, T.: Power Analysis Attacks: Revealing the Secrets of Smart Cards. Springer, New York (2007)"},{"issue":"1","key":"6_CR13","doi-asserted-by":"crossref","first-page":"3:1","DOI":"10.1145\/1502781.1502784","volume":"2","author":"RP McEvoy","year":"2009","unstructured":"McEvoy, R.P., Murphy, C.C., Marnane, W.P., Tunstall, M., Isolated, W.: A hiding countermeasure for differential power analysis on FPGAs. TRETS 2(1), 3:1\u20133:23 (2009)","journal-title":"TRETS"},{"key":"6_CR14","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"598","DOI":"10.1007\/978-3-662-44709-3_33","volume-title":"Cryptographic Hardware and Embedded Systems \u2013 CHES 2014","author":"A Moradi","year":"2014","unstructured":"Moradi, A., Immler, V.: Early propagation and imbalanced routing, how to diminish in FPGAs. In: Batina, L., Robshaw, M. (eds.) CHES 2014. LNCS, vol. 8731, pp. 598\u2013615. Springer, Heidelberg (2014). doi:\n10.1007\/978-3-662-44709-3_33"},{"key":"6_CR15","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1007\/978-3-642-40349-1_1","volume-title":"Cryptographic Hardware and Embedded Systems - CHES 2013","author":"A Moradi","year":"2013","unstructured":"Moradi, A., Mischke, O.: On the simplicity of converting leakages from multivariate to univariate. In: Bertoni, G., Coron, J.-S. (eds.) CHES 2013. LNCS, vol. 8086, pp. 1\u201320. Springer, Heidelberg (2013). doi:\n10.1007\/978-3-642-40349-1_1"},{"doi-asserted-by":"crossref","unstructured":"Moradi, A., Standaert, F.-X.: Moments-correlating DPA. In: Workshop on Theory of Implementation Security, TIS 2016, pp. 5\u201315. ACM (2016)","key":"6_CR16","DOI":"10.1145\/2996366.2996369"},{"key":"6_CR17","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"453","DOI":"10.1007\/978-3-662-48324-4_23","volume-title":"Cryptographic Hardware and Embedded Systems \u2013 CHES 2015","author":"A Moradi","year":"2015","unstructured":"Moradi, A., Wild, A.: Assessment of hiding the higher-order leakages in hardware. In: G\u00fcneysu, T., Handschuh, H. (eds.) CHES 2015. LNCS, vol. 9293, pp. 453\u2013474. Springer, Heidelberg (2015). doi:\n10.1007\/978-3-662-48324-4_23"},{"doi-asserted-by":"crossref","unstructured":"Nassar, M., Bhasin, S., Danger, J., Duc, G., Guilley, S.: BCDL: a high speed balanced DPL for FPGA with global precharge and no early evaluation. In: DATE 2010, pp. 849\u2013854. IEEE Computer Society (2010)","key":"6_CR18","DOI":"10.1109\/DATE.2010.5456932"},{"issue":"2","key":"6_CR19","doi-asserted-by":"crossref","first-page":"292","DOI":"10.1007\/s00145-010-9085-7","volume":"24","author":"S Nikova","year":"2011","unstructured":"Nikova, S., Rijmen, V., Schl\u00e4ffer, M.: Secure hardware implementation of nonlinear functions in the presence of glitches. J. Cryptol. 24(2), 292\u2013321 (2011)","journal-title":"J. Cryptol."},{"key":"6_CR20","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"81","DOI":"10.1007\/978-3-540-74735-2_6","volume-title":"Cryptographic Hardware and Embedded Systems - CHES 2007","author":"T Popp","year":"2007","unstructured":"Popp, T., Kirschbaum, M., Zefferer, T., Mangard, S.: Evaluation of the masked logic style MDPL on a prototype chip. In: Paillier, P., Verbauwhede, I. (eds.) CHES 2007. LNCS, vol. 4727, pp. 81\u201394. Springer, Heidelberg (2007). doi:\n10.1007\/978-3-540-74735-2_6"},{"key":"6_CR21","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"172","DOI":"10.1007\/11545262_13","volume-title":"Cryptographic Hardware and Embedded Systems \u2013 CHES 2005","author":"T Popp","year":"2005","unstructured":"Popp, T., Mangard, S.: Masked dual-rail pre-charge logic: DPA-resistance without routing constraints. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, vol. 3659, pp. 172\u2013186. Springer, Heidelberg (2005). doi:\n10.1007\/11545262_13"},{"doi-asserted-by":"crossref","unstructured":"Sauvage, L., Nassar, M., Guilley, S., Flament, F., Danger, J., Mathieu, Y.: DPL on Stratix II FPGA: what to expect? In: ReConFig 2009, pp. 243\u2013248. IEEE Computer Society (2009)","key":"6_CR22","DOI":"10.1109\/ReConFig.2009.58"},{"key":"6_CR23","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"495","DOI":"10.1007\/978-3-662-48324-4_25","volume-title":"Cryptographic Hardware and Embedded Systems \u2013 CHES 2015","author":"T Schneider","year":"2015","unstructured":"Schneider, T., Moradi, A.: Leakage assessment methodology. In: G\u00fcneysu, T., Handschuh, H. (eds.) CHES 2015. LNCS, vol. 9293, pp. 495\u2013513. Springer, Heidelberg (2015). doi:\n10.1007\/978-3-662-48324-4_25"},{"key":"6_CR24","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"443","DOI":"10.1007\/978-3-642-01001-9_26","volume-title":"Advances in Cryptology - EUROCRYPT 2009","author":"F-X Standaert","year":"2009","unstructured":"Standaert, F.-X., Malkin, T.G., Yung, M.: A unified framework for the analysis of side-channel key recovery attacks. In: Joux, A. (ed.) EUROCRYPT 2009. LNCS, vol. 5479, pp. 443\u2013461. Springer, Heidelberg (2009). doi:\n10.1007\/978-3-642-01001-9_26"},{"doi-asserted-by":"crossref","unstructured":"Suh, G.E., Devadas, S.: Physical unclonable functions for device authentication and secret key generation. In: Proceedings of the 44th Design Automation Conference - DAC 2007, San Diego, CA, USA, 4\u20138 June 2007, pp. 9\u201314. IEEE Computer Society (2007)","key":"6_CR25","DOI":"10.1145\/1278480.1278484"},{"issue":"1","key":"6_CR26","doi-asserted-by":"crossref","first-page":"109","DOI":"10.1109\/TC.2007.250627","volume":"56","author":"B Sunar","year":"2007","unstructured":"Sunar, B., Martin, W.J., Stinson, D.R.: A provably secure true random number generator with built-in tolerance to active attacks. IEEE Trans. Comput. 56(1), 109\u2013119 (2007)","journal-title":"IEEE Trans. Comput."},{"key":"6_CR27","first-page":"403","volume":"2002","author":"K Tiri","year":"2002","unstructured":"Tiri, K., Akmal, M., Verbauwhede, I.: A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards. ESSCIRC 2002, 403\u2013406 (2002)","journal-title":"ESSCIRC"},{"doi-asserted-by":"crossref","unstructured":"Tiri, K., Verbauwhede, I.: A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation. In: DATE 2004, pp. 246\u2013251. IEEE Computer Society (2004)","key":"6_CR28","DOI":"10.1109\/DATE.2004.1268856"},{"key":"6_CR29","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"81","DOI":"10.1007\/978-3-319-21476-4_6","volume-title":"Constructive Side-Channel Analysis and Secure Design","author":"A Wild","year":"2015","unstructured":"Wild, A., Moradi, A., G\u00fcneysu, T.: Evaluating the duplication of dual-rail precharge logics on FPGAs. In: Mangard, S., Poschmann, A.Y. (eds.) COSADE 2014. LNCS, vol. 9064, pp. 81\u201394. Springer, Cham (2015). doi:\n10.1007\/978-3-319-21476-4_6"},{"unstructured":"Wild, A., Moradi, A., Guneysu, T.: GliFreD: Glitch-Free Duplication - towards power-equalized circuits on FPGAs. IEEE Trans. Comput. (2017). \nhttp:\/\/doi.ieeecomputersociety.org\/10.1109\/TC.2017.2651829","key":"6_CR30"},{"unstructured":"Xilinx: UG472 7 series FPGAs clocking resources user guide, June 2015","key":"6_CR31"},{"doi-asserted-by":"crossref","unstructured":"Yu, P., Schaumont, P.: Secure FPGA circuits using controlled placement and routing. In: CODES+ISSS 2007, pp. 45\u201350 (2007)","key":"6_CR32","DOI":"10.1145\/1289816.1289831"}],"container-title":["Lecture Notes in Computer Science","Constructive Side-Channel Analysis and Secure Design"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-319-64647-3_6","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,7,28]],"date-time":"2017-07-28T15:35:21Z","timestamp":1501256121000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-319-64647-3_6"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017]]},"ISBN":["9783319646466","9783319646473"],"references-count":32,"URL":"https:\/\/doi.org\/10.1007\/978-3-319-64647-3_6","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2017]]}}}