{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,10]],"date-time":"2026-02-10T20:00:57Z","timestamp":1770753657189,"version":"3.50.0"},"publisher-location":"Cham","reference-count":17,"publisher":"Springer International Publishing","isbn-type":[{"value":"9783319647005","type":"print"},{"value":"9783319647012","type":"electronic"}],"license":[{"start":{"date-parts":[[2017,1,1]],"date-time":"2017-01-01T00:00:00Z","timestamp":1483228800000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017]]},"DOI":"10.1007\/978-3-319-64701-2_20","type":"book-chapter","created":{"date-parts":[[2017,7,25]],"date-time":"2017-07-25T08:56:55Z","timestamp":1500973015000},"page":"273-287","source":"Crossref","is-referenced-by-count":29,"title":["Implementation of Bitsliced AES Encryption on CUDA-Enabled GPU"],"prefix":"10.1007","author":[{"given":"Naoki","family":"Nishikawa","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hideharu","family":"Amano","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Keisuke","family":"Iwai","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2017,7,26]]},"reference":[{"key":"20_CR1","doi-asserted-by":"crossref","first-page":"3633","DOI":"10.1002\/cpe.3358","volume":"27","author":"G Agosta","year":"2015","unstructured":"Agosta, G., Barenghi, A., Federico, A.D., Pelosi, G.: OpenCL performance portability for general-purpose computation on graphics processor units: an exploration on cryptographic primitives. Concurrency Comput. Pract. Experience 27, 3633\u20133660 (2015)","journal-title":"Concurrency Comput. Pract. Experience"},{"key":"20_CR2","doi-asserted-by":"crossref","unstructured":"Biagio, A.D., Barenghi, A., Agosta, G., Pelosi, G.: Design of a parallel AES for graphics hardware using the CUDA framework. In: Proceedings of the 2009 International Symposium on Parallel Distributed Processing (2009)","DOI":"10.1109\/IPDPS.2009.5161242"},{"issue":"1","key":"20_CR3","doi-asserted-by":"crossref","first-page":"131","DOI":"10.15803\/ijnc.2.1_131","volume":"2","author":"K Iwai","year":"2012","unstructured":"Iwai, K., Nishikawa, N., Kurokawa, T.: Acceleration of AES encryption on CUDA GPU. Int. J. Netw. Comput. 2(1), 131\u2013145 (2012)","journal-title":"Int. J. Netw. Comput."},{"key":"20_CR4","doi-asserted-by":"crossref","unstructured":"Li, Q., Zhong, C., Zhao, K., Mei, X., Chu, X.: Implementation and analysis of AES encryption on GPU. In: Proceedings of the 14th International Conference on High Performance Computing and Communication (2012)","DOI":"10.1109\/HPCC.2012.119"},{"key":"20_CR5","unstructured":"Fomin, D.: A timing attack on CUDA implementations of an AES-type block cipher. In: Proceedings of 4th Workshop on Current Trends in Cryptology (2015)"},{"key":"20_CR6","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"260","DOI":"10.1007\/BFb0052352","volume-title":"Fast Software Encryption","author":"E Biham","year":"1997","unstructured":"Biham, E.: A fast new DES implementation in software. In: Biham, E. (ed.) FSE 1997. LNCS, vol. 1267, pp. 260\u2013272. Springer, Heidelberg (1997). doi:\n10.1007\/BFb0052352"},{"key":"20_CR7","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1007\/978-3-642-04138-9_1","volume-title":"Cryptographic Hardware and Embedded Systems - CHES 2009","author":"E K\u00e4sper","year":"2009","unstructured":"K\u00e4sper, E., Schwabe, P.: Faster and timing-attack resistant AES-GCM. In: Clavier, C., Gaj, K. (eds.) CHES 2009. LNCS, vol. 5747, pp. 1\u201317. Springer, Heidelberg (2009). doi:\n10.1007\/978-3-642-04138-9_1"},{"key":"20_CR8","unstructured":"NVIDIA Corp. GP100 Pascal Whitepaper (2016)"},{"key":"20_CR9","volume-title":"The CUDA Handbook","author":"N Wilt","year":"2013","unstructured":"Wilt, N.: The CUDA Handbook. Pearson Education, Upper Saddle River (2013)"},{"issue":"6","key":"20_CR10","doi-asserted-by":"crossref","first-page":"1506","DOI":"10.1587\/transinf.E97.D.1506","volume":"97","author":"N Nishikawa","year":"2014","unstructured":"Nishikawa, N., Iwai, K., Tanaka, H., Kurokawa, T.: Throughput and power efficiency evaluation of block ciphers on Kepler and GCN GPUs using micro-benchmark analysis. IEICE Trans. Inf. Syst. 97(6), 1506\u20131515 (2014)","journal-title":"IEICE Trans. Inf. Syst."},{"key":"20_CR11","unstructured":"Bruna, J.V.D., Regazzoni, F., Tumeo, A.: Bitsliced Implementation of the AES Algorithm on GPU. In: Design, Automation and Test in Europe 2012 - Applications for Many-Core Poster Session (2012)"},{"key":"20_CR12","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"125","DOI":"10.1007\/978-3-662-49301-4_8","volume-title":"The New Codebreakers","author":"RK Lim","year":"2016","unstructured":"Lim, R.K., Petzold, L.R., Ko\u00e7, \u00c7.K.: Bitsliced high-performance AES-ECB on GPUs. In: Ryan, P.Y.A., Naccache, D., Quisquater, J.-J. (eds.) The New Codebreakers. LNCS, vol. 9100, pp. 125\u2013133. Springer, Heidelberg (2016). doi:\n10.1007\/978-3-662-49301-4_8"},{"key":"20_CR13","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"187","DOI":"10.1007\/978-3-540-79263-5_12","volume-title":"Topics in Cryptology \u2013 CT-RSA 2008","author":"R K\u00f6nighofer","year":"2008","unstructured":"K\u00f6nighofer, R.: A fast and cache-timing resistant implementation of the AES. In: Malkin, T. (ed.) CT-RSA 2008. LNCS, vol. 4964, pp. 187\u2013202. Springer, Heidelberg (2008). doi:\n10.1007\/978-3-540-79263-5_12"},{"key":"20_CR14","series-title":"IFIP Advances in Information and Communication Technology","doi-asserted-by":"publisher","first-page":"287","DOI":"10.1007\/978-3-642-30436-1_24","volume-title":"Information Security and Privacy Research","author":"J Boyar","year":"2012","unstructured":"Boyar, J., Peralta, R.: A small depth-16 circuit for the AES S-Box. In: Gritzalis, D., Furnell, S., Theoharidou, M. (eds.) SEC 2012. IAICT, vol. 376, pp. 287\u2013298. Springer, Heidelberg (2012). doi:\n10.1007\/978-3-642-30436-1_24"},{"issue":"2","key":"20_CR15","doi-asserted-by":"crossref","first-page":"251","DOI":"10.15803\/ijnc.2.2_251","volume":"2","author":"N Nishikawa","year":"2012","unstructured":"Nishikawa, N., Iwai, K., Kurokawa, T.: Acceleration of AES encryption on CUDA GPU. Int. J. Netw. Comput. 2(2), 251\u2013268 (2012)","journal-title":"Int. J. Netw. Comput."},{"key":"20_CR16","unstructured":"OpenMP Architecture Review Board. OpenMP Application Program Interface"},{"key":"20_CR17","unstructured":"NVIDIA Corp. Whitepaper: NVIDIA NVLink High-Speed Interconnect: Application Performance (2014)"}],"container-title":["Lecture Notes in Computer Science","Network and System Security"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-319-64701-2_20","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,7,25]],"date-time":"2017-07-25T09:04:32Z","timestamp":1500973472000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-319-64701-2_20"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017]]},"ISBN":["9783319647005","9783319647012"],"references-count":17,"URL":"https:\/\/doi.org\/10.1007\/978-3-319-64701-2_20","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"value":"0302-9743","type":"print"},{"value":"1611-3349","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017]]}}}