{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,27]],"date-time":"2026-03-27T17:11:52Z","timestamp":1774631512101,"version":"3.50.1"},"publisher-location":"Cham","reference-count":20,"publisher":"Springer International Publishing","isbn-type":[{"value":"9783319667867","type":"print"},{"value":"9783319667874","type":"electronic"}],"license":[{"start":{"date-parts":[[2017,1,1]],"date-time":"2017-01-01T00:00:00Z","timestamp":1483228800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2017,1,1]],"date-time":"2017-01-01T00:00:00Z","timestamp":1483228800000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017]]},"DOI":"10.1007\/978-3-319-66787-4_10","type":"book-chapter","created":{"date-parts":[[2017,8,24]],"date-time":"2017-08-24T13:06:02Z","timestamp":1503579962000},"page":"189-210","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":108,"title":["Novel Bypass Attack and BDD-based Tradeoff Analysis Against All Known Logic Locking\u00a0Attacks"],"prefix":"10.1007","author":[{"given":"Xiaolin","family":"Xu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bicky","family":"Shakya","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mark M.","family":"Tehranipoor","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Domenic","family":"Forte","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2017,8,25]]},"reference":[{"key":"10_CR1","doi-asserted-by":"crossref","unstructured":"Tehranipoor, M.M., Guin, U., Forte, U.: Counterfeit integrated circuits. In: Counterfeit Integrated Circuits, pp. 15\u201336. Springer, Heidelberg (2015)","DOI":"10.1007\/978-3-319-11824-6_2"},{"key":"10_CR2","doi-asserted-by":"crossref","unstructured":"Vaidyanathan, K., Liu, R., Sumbul, E., Zhu, Q., Franchetti, F., Pileggi, L.: Efficient and secure intellectual property (IP) design with split fabrication. In: 2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), pp. 13\u201318. IEEE (2014)","DOI":"10.1109\/HST.2014.6855561"},{"key":"10_CR3","unstructured":"Alkabani, Y., Koushanfar, F.: Active hardware metering for intellectual property protection and security. In: USENIX security, Boston MA, USA, pp. 291\u2013306 (2007)"},{"key":"10_CR4","doi-asserted-by":"crossref","unstructured":"Roy, J.A., Koushanfar, F., Markov, I.L.: Epic: Ending piracy of integrated circuits, vol. 43, pp. 30\u201338. IEEE (2010)","DOI":"10.1109\/MC.2010.284"},{"issue":"2","key":"10_CR5","doi-asserted-by":"publisher","first-page":"410","DOI":"10.1109\/TC.2013.193","volume":"64","author":"J Rajendran","year":"2015","unstructured":"Rajendran, J., Zhang, H., Zhang, C., Rose, G.S., Pino, Y., Sinanoglu, O., Karri, R.: Fault analysis-based logic encryption. IEEE Trans. Comput. 64(2), 410\u2013424 (2015)","journal-title":"IEEE Trans. Comput."},{"key":"10_CR6","doi-asserted-by":"crossref","unstructured":"Subramanyan, P., Ray, S., Malik, S.: Evaluating the security of logic encryption algorithms. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137\u2013143. IEEE (2015)","DOI":"10.1109\/HST.2015.7140252"},{"key":"10_CR7","doi-asserted-by":"crossref","unstructured":"Yasin, M., Mazumdar, B., Rajendran, J.J.V., Sinanoglu, O.: SARLock: SAT attack resistant logic locking. In: 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 236\u2013241, May 2016","DOI":"10.1109\/HST.2016.7495588"},{"key":"10_CR8","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"127","DOI":"10.1007\/978-3-662-53140-2_7","volume-title":"Cryptographic Hardware and Embedded Systems \u2013 CHES 2016","author":"Y Xie","year":"2016","unstructured":"Xie, Y., Srivastava, A.: Mitigating SAT attack on logic locking. In: Gierlichs, B., Poschmann, A.Y. (eds.) CHES 2016. LNCS, vol. 9813, pp. 127\u2013146. Springer, Heidelberg (2016). doi:\n                      10.1007\/978-3-662-53140-2_7"},{"key":"10_CR9","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"363","DOI":"10.1007\/978-3-642-04138-9_26","volume-title":"Cryptographic Hardware and Embedded Systems - CHES 2009","author":"R Torrance","year":"2009","unstructured":"Torrance, R., James, D.: The state-of-the-art in IC reverse engineering. In: Clavier, C., Gaj, K. (eds.) CHES 2009. LNCS, vol. 5747, pp. 363\u2013381. Springer, Heidelberg (2009). doi:\n                      10.1007\/978-3-642-04138-9_26"},{"key":"10_CR10","doi-asserted-by":"crossref","unstructured":"Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Security analysis of logic obfuscation. In: Proceedings of the 49th Annual Design Automation Conference, pp. 83\u201389. ACM (2012)","DOI":"10.1145\/2228360.2228377"},{"key":"10_CR11","volume-title":"Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits","author":"M Bushnell","year":"2004","unstructured":"Bushnell, M., Agrawal, V.: Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, vol. 17. Springer, Heidelberg (2004)"},{"issue":"9","key":"10_CR12","doi-asserted-by":"publisher","first-page":"1411","DOI":"10.1109\/TCAD.2015.2511144","volume":"35","author":"M Yasin","year":"2016","unstructured":"Yasin, M., Rajendran, J.J., Sinanoglu, O., Karri, R.: On improving the security of logic locking. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 35(9), 1411\u20131424 (2016)","journal-title":"IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."},{"key":"10_CR13","doi-asserted-by":"crossref","unstructured":"Yasin, M., Mazumdar, B., Sinanoglu, O., Rajendran, J.: Security analysis of anti-SAT. In: 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 342\u2013347. IEEE (2017)","DOI":"10.1109\/ASPDAC.2017.7858346"},{"key":"10_CR14","doi-asserted-by":"crossref","unstructured":"Shen, Y., Zhou, H.: Double DIP: Re-evaluating security of logic encryption algorithms. In: Proceedings of the Great Lakes Symposium on VLSI 2017, GLSVLSI 2017, pp. 179\u2013184. ACM, New York (2017)","DOI":"10.1145\/3060403.3060469"},{"key":"10_CR15","unstructured":"Brglez, F.: A neutral netlist of 10 combinational benchmark circuits and a target translation in FORTRAN. In: ISCAS-85 (1985)"},{"key":"10_CR16","unstructured":"Amar\u00fa, L., Gaillardon, P.-E., De Micheli, G.: The EPFL combinational benchmark suite. In: Proceedings of the 24th International Workshop on Logic & Synthesis (IWLS), number EPFL-CONF-207551 (2015)"},{"key":"10_CR17","unstructured":"Soos, M.: Cryptominisat-a SAT solver for cryptographic problems (2009). \n                      http:\/\/www.msoos.org\/cryptominisat4"},{"key":"10_CR18","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"24","DOI":"10.1007\/978-3-642-14295-6_5","volume-title":"Computer Aided Verification","author":"R Brayton","year":"2010","unstructured":"Brayton, R., Mishchenko, A.: ABC: An academic industrial-strength verification tool. In: Touili, T., Cook, B., Jackson, P. (eds.) CAV 2010. LNCS, vol. 6174, pp. 24\u201340. Springer, Heidelberg (2010). doi:\n                      10.1007\/978-3-642-14295-6_5"},{"key":"10_CR19","unstructured":"Somenzi, F.: CUDD: CU decision diagram package release 2.3.0. University of Colorado at Boulder (1998)"},{"issue":"7","key":"10_CR20","doi-asserted-by":"publisher","first-page":"866","DOI":"10.1109\/TCAD.2002.1013899","volume":"21","author":"C Yang","year":"2002","unstructured":"Yang, C., Ciesielski, M.: BDS: A BDD-based logic optimization system. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 21(7), 866\u2013876 (2002)","journal-title":"IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."}],"container-title":["Lecture Notes in Computer Science","Cryptographic Hardware and Embedded Systems \u2013 CHES 2017"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-319-66787-4_10","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,9,18]],"date-time":"2020-09-18T00:04:09Z","timestamp":1600387449000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-319-66787-4_10"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017]]},"ISBN":["9783319667867","9783319667874"],"references-count":20,"URL":"https:\/\/doi.org\/10.1007\/978-3-319-66787-4_10","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"value":"0302-9743","type":"print"},{"value":"1611-3349","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017]]},"assertion":[{"value":"25 August 2017","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"CHES","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"International Conference on Cryptographic Hardware and Embedded Systems","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Taipei","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Taiwan","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2017","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"25 September 2017","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"28 September 2017","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"ches2017","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"https:\/\/ches.iacr.org\/2017\/","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"This content has been made available to all.","name":"free","label":"Free to read"}]}}