{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,9]],"date-time":"2024-09-09T22:20:45Z","timestamp":1725920445472},"publisher-location":"Cham","reference-count":10,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783319672946"},{"type":"electronic","value":"9783319672953"}],"license":[{"start":{"date-parts":[[2017,11,16]],"date-time":"2017-11-16T00:00:00Z","timestamp":1510790400000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018]]},"DOI":"10.1007\/978-3-319-67295-3_5","type":"book-chapter","created":{"date-parts":[[2017,11,15]],"date-time":"2017-11-15T07:36:44Z","timestamp":1510731404000},"page":"103-124","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Identifying Transparent Logic in Gate-Level Circuits"],"prefix":"10.1007","author":[{"given":"Yu-Yun","family":"Dai","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Robert K.","family":"Brayton","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2017,11,16]]},"reference":[{"key":"5_CR1","doi-asserted-by":"crossref","DOI":"10.1093\/acprof:oso\/9780198568612.001.0001","volume-title":"Category Theory","author":"S Awodey","year":"2006","unstructured":"S. Awodey, Category Theory (Clarendon Press, Oxford University Press, Oxford, New York, 2006)"},{"key":"5_CR2","first-page":"24","volume-title":"Abc: an academic industrial-strength verification tool, in Computer Aided Verification","author":"R Brayton","year":"2010","unstructured":"R. Brayton, A. Mishchenko, Abc: an academic industrial-strength verification tool, in Computer Aided Verification (Springer, Berlin, 2010), pp. 24\u201340"},{"key":"5_CR3","doi-asserted-by":"crossref","first-page":"135","DOI":"10.3233\/SAT190106","volume":"9","author":"G Cabodi","year":"2016","unstructured":"G. Cabodi, C. Loiacono, M. Palena, P. Pasini, D. Patti, S. Quer, D. Vendraminetto, A. Biere, K. Heljanko, Hardware model checking competition 2014: an analysis and comparison of solvers and benchmarks. J. Satisfiability Boolean Model. Comput. 9, 135\u2013172 (2016)","journal-title":"J. Satisfiability Boolean Model. Comput."},{"key":"5_CR4","volume-title":"Sequential equivalence checking of clock-gated circuits, in Design Automation Conference","author":"YY Dai","year":"2015","unstructured":"Y.Y. Dai, K.Y. Khoo, R. Brayton, Sequential equivalence checking of clock-gated circuits, in Design Automation Conference (ACM, New York, 2015)"},{"issue":"3","key":"5_CR5","doi-asserted-by":"crossref","first-page":"72","DOI":"10.1109\/54.785838","volume":"16","author":"MC Hansen","year":"1999","unstructured":"M.C. Hansen, H. Yalcin, J.P. Hayes, Unveiling the iscas-85 benchmarks: a case study in reverse engineering. IEEE Des. Test Comput. 16(3), 72\u201380 (1999)","journal-title":"IEEE Des. Test Comput."},{"key":"5_CR6","doi-asserted-by":"crossref","DOI":"10.21236\/ADA623698","volume-title":"Formal methods for reverse engineering gate-level netlists","author":"W Li","year":"2013","unstructured":"W. Li, Formal methods for reverse engineering gate-level netlists. Master\u2019s thesis, University of California, Berkeley (2013)"},{"key":"5_CR7","first-page":"67","volume-title":"Wordrev: finding word-level structures in a sea of bit-level gates, in 2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","author":"W Li","year":"2013","unstructured":"W. Li, G. Adria, P. Subramanyan, W.Y. Tan, A. Tiwari, S. Malik, N. Shankar, S. Seshia, Wordrev: finding word-level structures in a sea of bit-level gates, in 2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) (IEEE, New York, 2013), pp. 67\u201374"},{"key":"5_CR8","unstructured":"M. Soeken, B. Sterin, R. Drechsler, and R. Brayton, \u201cSimulation graphs for reverse engineering,\u201d in FMCAD, (2015), pp. 152\u2013159."},{"key":"5_CR9","volume-title":"Heuristic NPN classification for large functions using AIGs and LEXSAT, in International Conference on Theory and Applications of Satisfiability Testing (SAT)","author":"M Soeken","year":"2016","unstructured":"M. Soeken, A. Mishchenko, A. Petkovska, B. Sterin, P. Ienne, R.K. Brayton, G.D. Micheli, Heuristic NPN classification for large functions using AIGs and LEXSAT, in International Conference on Theory and Applications of Satisfiability Testing (SAT) (2016)"},{"issue":"1","key":"5_CR10","doi-asserted-by":"crossref","first-page":"63","DOI":"10.1109\/TETC.2013.2294918","volume":"2","author":"P Subramanyan","year":"2014","unstructured":"P. Subramanyan, N. Tsiskaridze, W. Li, A. Gascon, W.Y. Tan, A. Tiwari, N. Shankar, S. Seshia, S. Malik, Reverse engineering digital circuits using structural and functional analyses. IEEE Trans. Emerg. Top. Comput. 2(1), 63\u201380 (2014)","journal-title":"IEEE Trans. Emerg. Top. Comput."}],"container-title":["Advanced Logic Synthesis"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-319-67295-3_5","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,10,21]],"date-time":"2020-10-21T18:02:09Z","timestamp":1603303329000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-319-67295-3_5"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,11,16]]},"ISBN":["9783319672946","9783319672953"],"references-count":10,"URL":"https:\/\/doi.org\/10.1007\/978-3-319-67295-3_5","relation":{},"subject":[],"published":{"date-parts":[[2017,11,16]]}}}