{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,26]],"date-time":"2025-06-26T04:09:20Z","timestamp":1750910960891,"version":"3.41.0"},"publisher-location":"Cham","reference-count":18,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783319682099"},{"type":"electronic","value":"9783319682105"}],"license":[{"start":{"date-parts":[[2017,1,1]],"date-time":"2017-01-01T00:00:00Z","timestamp":1483228800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2017,1,1]],"date-time":"2017-01-01T00:00:00Z","timestamp":1483228800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017]]},"DOI":"10.1007\/978-3-319-68210-5_8","type":"book-chapter","created":{"date-parts":[[2017,9,18]],"date-time":"2017-09-18T05:58:09Z","timestamp":1505714289000},"page":"87-99","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Improving Branch Prediction for Thread Migration on Multi-core Architectures"],"prefix":"10.1007","author":[{"given":"Tan","family":"Zhang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chaobing","family":"Zhou","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Libo","family":"Huang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nong","family":"Xiao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sheng","family":"Ma","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2017,9,19]]},"reference":[{"issue":"1","key":"8_CR1","doi-asserted-by":"publisher","first-page":"53","DOI":"10.1109\/L-CA.2012.30","volume":"13","author":"KS Shim","year":"2014","unstructured":"Shim, K.S., Lis, M., Khan, O., Devadas, S.: Thread migration prediction for distributed shared caches. IEEE Comput. Architect. Lett. 13(1), 53\u201356 (2014)","journal-title":"IEEE Comput. Architect. Lett."},{"issue":"4","key":"8_CR2","doi-asserted-by":"publisher","first-page":"80","DOI":"10.1145\/1105734.1105745","volume":"33","author":"T Constantinou","year":"2005","unstructured":"Constantinou, T., Sazeides, Y., Michaud, P., Fetis, D., Seznec, A.: Performance implications of single thread migration on a chip multi-core. ACM SIGARCH Comput. Architect. News 33(4), 80\u201391 (2005)","journal-title":"ACM SIGARCH Comput. Architect. News"},{"issue":"2","key":"8_CR3","doi-asserted-by":"publisher","first-page":"125","DOI":"10.1145\/1353535.1346298","volume":"42","author":"B Choi","year":"2008","unstructured":"Choi, B., Porter, L., Tullsen, D.M.: Accurate branch prediction for short threads. ACM SIGOPS Oper. Syst. Rev. 42(2), 125\u2013134 (2008)","journal-title":"ACM SIGOPS Oper. Syst. Rev."},{"key":"8_CR4","doi-asserted-by":"crossref","unstructured":"Weissman, B., Gomes, B., Quittek, J., Holtkamp, M.: Efficient fine-grain thread migration with active threads. In: Parallel Processing Symposium, IPPS\/SPDP 1998, vol. 17, pp. 410\u2013414 (1998)","DOI":"10.1109\/IPPS.1998.669949"},{"issue":"2","key":"8_CR5","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/2024716.2024718","volume":"39","author":"N Binkert","year":"2011","unstructured":"Binkert, N., Beckmann, B., Black, G., Reinhardt, S.K., Saidi, A., Basu, A., Hestness, J., Hower, D.R., Krishna, T., Sardashti, S., et al.: The gem5 simulator. ACM SIGARCH Comput. Architect. News 39(2), 1\u20137 (2011)","journal-title":"ACM SIGARCH Comput. Architect. News"},{"key":"8_CR6","unstructured":"CBP2014: https:\/\/www.jilp.org\/cbp2014\/"},{"key":"8_CR7","unstructured":"Seznec, A.: TAGE-SC-L branch predictors. JILP - Championship Branch Prediction (2014)"},{"key":"8_CR8","doi-asserted-by":"crossref","unstructured":"Zhou, C., Huang, L., Li, Z., Zhang, T., Dou, Q.: Design space exploration of TAGE branch predictor with ultra-small RAM. In: The 27th Edition of the ACM Great Lakes Symposium on VLSI (GLSVLSI). ACM (2017)","DOI":"10.1145\/3060403.3060423"},{"key":"8_CR9","doi-asserted-by":"crossref","unstructured":"Chen, J., Shen, L., Wang, Z., Li, N., Xu, Y.: Dynamic power-performance adjustment on clustered multi-threading processors. In: 2016 IEEE International Conference on Networking, Architecture and Storage (NAS), pp. 1\u20132. IEEE (2016)","DOI":"10.1109\/NAS.2016.7549399"},{"issue":"1","key":"8_CR10","doi-asserted-by":"publisher","first-page":"12","DOI":"10.1109\/L-CA.2002.7","volume":"1","author":"KA Shaw","year":"2002","unstructured":"Shaw, K.A., Dally, W.J.: Migration in single chip multiprocessors. IEEE Comput. Architect. Lett. 1(1), 12 (2002)","journal-title":"IEEE Comput. Architect. Lett."},{"issue":"1","key":"8_CR11","doi-asserted-by":"publisher","first-page":"32","DOI":"10.1109\/TSE.1987.232563","volume":"SE\u201313","author":"FCH Lin","year":"1987","unstructured":"Lin, F.C.H., Keller, R.M.: The gradient model load balancing method. IEEE Trans. Softw. Eng. SE\u201313(1), 32\u201338 (1987)","journal-title":"IEEE Trans. Softw. Eng."},{"issue":"4","key":"8_CR12","doi-asserted-by":"publisher","first-page":"319","DOI":"10.1007\/BF03356753","volume":"24","author":"HHJ Hum","year":"1996","unstructured":"Hum, H.H.J., Maquelin, O., Theobald, K.B., Tian, X., Gao, G.R., Hendren, L.J.: A study of the earth-manna multithreaded system. Int. J. Parallel Program. 24(4), 319\u2013348 (1996)","journal-title":"Int. J. Parallel Program."},{"key":"8_CR13","doi-asserted-by":"crossref","unstructured":"St. Amant, R., Jimenez, D.A., Burger, D.: Low-power, high-performance analog neural branch prediction. In: IEEE\/ACM International Symposium on Microarchitecture, pp. 447\u2013458 (2008)","DOI":"10.1109\/MICRO.2008.4771812"},{"key":"8_CR14","unstructured":"Ishii, Y., Kuroyanagi, K., Sawada, T., Inaba, M., Hiraki, K.: Revisiting local history to improve the fused two-level branch predictor (2010)"},{"key":"8_CR15","first-page":"1","volume":"8","author":"A Seznec","year":"2006","unstructured":"Seznec, A., Michaud, P.: A case for (partially) tagged geometric history length branch prediction. J. Instr. Level Parallelism 8, 1\u201323 (2006)","journal-title":"J. Instr. Level Parallelism"},{"key":"8_CR16","doi-asserted-by":"crossref","unstructured":"Seznec, A., Miguel, J.S., Albericio, J.: The inner most loop iteration counter: a new dimension in branch history. In: International Symposium on Microarchitecture, pp. 347\u2013357 (2015)","DOI":"10.1145\/2830772.2830831"},{"key":"8_CR17","doi-asserted-by":"crossref","unstructured":"Seznec, A.: A new case for the TAGE branch predictor. In: IEEE\/ACM International Symposium on Microarchitecture, pp. 117\u2013127 (2011)","DOI":"10.1145\/2155620.2155635"},{"key":"8_CR18","doi-asserted-by":"crossref","unstructured":"Kaynak, C., Grot, B., Falsafi, B.: Shift: shared history instruction fetch for lean-core server processors. In: IEEE\/ACM International Symposium on Microarchitecture, pp. 272\u2013283 (2013)","DOI":"10.1145\/2540708.2540732"}],"container-title":["Lecture Notes in Computer Science","Network and Parallel Computing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-319-68210-5_8","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,25]],"date-time":"2025-06-25T19:45:46Z","timestamp":1750880746000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-319-68210-5_8"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017]]},"ISBN":["9783319682099","9783319682105"],"references-count":18,"URL":"https:\/\/doi.org\/10.1007\/978-3-319-68210-5_8","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2017]]},"assertion":[{"value":"19 September 2017","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"NPC","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"IFIP International Conference on Network and Parallel Computing","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Hefei","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"China","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2017","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"20 October 2017","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"21 October 2017","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"14","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"npc2017","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"http:\/\/npc-china2017.org\/","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"This content has been made available to all.","name":"free","label":"Free to read"}]}}