{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,10]],"date-time":"2024-09-10T05:24:01Z","timestamp":1725945841897},"publisher-location":"Cham","reference-count":15,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783319734460"},{"type":"electronic","value":"9783319734477"}],"license":[{"start":{"date-parts":[[2018,1,1]],"date-time":"2018-01-01T00:00:00Z","timestamp":1514764800000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018]]},"DOI":"10.1007\/978-3-319-73447-7_37","type":"book-chapter","created":{"date-parts":[[2018,1,20]],"date-time":"2018-01-20T00:23:18Z","timestamp":1516407798000},"page":"333-342","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["A Virtual Channel Allocation Algorithm for NoC"],"prefix":"10.1007","author":[{"given":"Dongxing","family":"Bao","sequence":"first","affiliation":[]},{"given":"Xiaoming","family":"Li","sequence":"additional","affiliation":[]},{"given":"Yizong","family":"Xin","sequence":"additional","affiliation":[]},{"given":"Jiuru","family":"Yang","sequence":"additional","affiliation":[]},{"given":"Xiangshi","family":"Ren","sequence":"additional","affiliation":[]},{"given":"Fangfa","family":"Fu","sequence":"additional","affiliation":[]},{"given":"Cheng","family":"Liu","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2018,1,21]]},"reference":[{"issue":"4","key":"37_CR1","doi-asserted-by":"crossref","first-page":"490","DOI":"10.1109\/5.920580","volume":"89","author":"R Ho","year":"2001","unstructured":"Ho, R., Mai, K., Horowitz, M.: The future of wires. Proc. IEEE 89(4), 490\u2013504 (2001)","journal-title":"Proc. IEEE"},{"key":"37_CR2","doi-asserted-by":"crossref","unstructured":"Dally, W.J., Towles, B.: Route packets, not wires: on-chip interconnection networks. In: The 38th Design Automation Conference, pp. 684\u2013689 (2001)","DOI":"10.1109\/DAC.2001.935594"},{"issue":"1","key":"37_CR3","first-page":"70","volume":"35","author":"L Benini","year":"2002","unstructured":"Benini, L., De Micheli, G.: Networks on chips: a new SoC paradigm. IEEE Trans. Comput. 35(1), 70\u201378 (2002)","journal-title":"IEEE Trans. Comput."},{"key":"37_CR4","doi-asserted-by":"crossref","unstructured":"Guerrier, P., Greiner, A.: A generic architecture for on-chip packet-switched interconnections. In: Design Automation and Test in Europe (DATE 2000), pp. 250\u2013256 (2000)","DOI":"10.1145\/343647.343776"},{"issue":"3","key":"37_CR5","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/1132952.1132953","volume":"38","author":"T Bjerregaard","year":"2006","unstructured":"Bjerregaard, T., Mahadevan, S.: A survey of research and practices of network-on-chip. ACM Comput. Surv. 38(3), 1\u201351 (2006)","journal-title":"ACM Comput. Surv."},{"key":"37_CR6","doi-asserted-by":"crossref","unstructured":"Kim, J., Nicopoulos, C., Park, D., et al.: A gracefully degrading and energy-efficient modular router architecture for on-chip networks. In: The 33rd International Symposium on Computer Architecture (ISCA 2006), pp. 4\u201315 (2006)","DOI":"10.1145\/1150019.1136487"},{"key":"37_CR7","unstructured":"Hu, J., Marculescu, R.: Application-specific buffer space allocation for networks-on-chip router design. In: The IEEE\/ACM International Conference on Computer Aided Design (ICCAD), pp. 354\u2013361 (2004)"},{"key":"37_CR8","doi-asserted-by":"crossref","unstructured":"Nicopoulos, C.A., Park, D., Kim, J., et al.: VichaR: a dynamic virtual channel regulator for network-on-chip routers. In: The 39th Annual IEEE\/ACM International Symposium on Microarchitecture, pp. 333\u2013344 (2006)","DOI":"10.1109\/MICRO.2006.50"},{"key":"37_CR9","doi-asserted-by":"crossref","unstructured":"Chen, X., Peh, L.-S.: Leakage power modeling and optimization in interconnection networks. In: The International Symposium on Low Power Electronics and Design, pp. 90\u201395 (2003)","DOI":"10.1145\/871506.871531"},{"key":"37_CR10","doi-asserted-by":"crossref","unstructured":"Matsutani, H., Koibuchi, M., Wang, D., Amano, H.: Run-time power gating of on-chip routers using look-ahead routing. In: Design Automation Conference (ASPDAC), pp. 55\u201360 (2008)","DOI":"10.1109\/ASPDAC.2008.4484015"},{"key":"37_CR11","doi-asserted-by":"crossref","unstructured":"Matsutani, H., Koibuchi, M., Wang, D., Amano, H.: Adding slow-slient virtual channels for low-power on-chip networks. In: The 2nd IEEE International Symposium on Networks-On-Chip, pp. 23\u201332 (2008)","DOI":"10.1109\/NOCS.2008.4492722"},{"issue":"11","key":"37_CR12","doi-asserted-by":"crossref","first-page":"1115","DOI":"10.1080\/00207729708929472","volume":"28","author":"J Ding","year":"1997","unstructured":"Ding, J., Bhuyan, L.N.: Evaluation of multi-queue buffered multistage interconnection networks under uniform and non-uniform traffic patterns. Int. J. Syst. Sci. 28(11), 1115\u20131128 (1997)","journal-title":"Int. J. Syst. Sci."},{"key":"37_CR13","doi-asserted-by":"crossref","unstructured":"Ni, N., Pirvu, M., Bhuyan, L.: Circular buffered switch design with wormhole routing and virtual channels. In: Computer Design: VLSI in Computers and Processors, pp. 466\u2013473 (1998)","DOI":"10.1109\/ICCD.1998.727090"},{"issue":"2\u20133","key":"37_CR14","doi-asserted-by":"crossref","first-page":"105","DOI":"10.1016\/j.sysarc.2003.07.004","volume":"50","author":"E Bolotin","year":"2004","unstructured":"Bolotin, E., Cidon, I., Ginosar, R., Kolodny, A.: QNoC: QoS architecture and design process for network on chip. Spec. Issue Netw. Chip J. Syst. Architect. 50(2\u20133), 105\u2013128 (2004)","journal-title":"Spec. Issue Netw. Chip J. Syst. Architect."},{"key":"37_CR15","doi-asserted-by":"crossref","unstructured":"Huang, T., Ogras, U.Y., Marculescu, R.: Virtual channels planning for networks-on-chip. In: Proceedings of the 8th International on Quality Electronic Design (ISQED), pp. 879\u2013884 (2007)","DOI":"10.1109\/ISQED.2007.169"}],"container-title":["Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering","Machine Learning and Intelligent Communications"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-319-73447-7_37","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,10,9]],"date-time":"2019-10-09T12:19:03Z","timestamp":1570623543000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-319-73447-7_37"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018]]},"ISBN":["9783319734460","9783319734477"],"references-count":15,"URL":"https:\/\/doi.org\/10.1007\/978-3-319-73447-7_37","relation":{},"ISSN":["1867-8211","1867-822X"],"issn-type":[{"type":"print","value":"1867-8211"},{"type":"electronic","value":"1867-822X"}],"subject":[],"published":{"date-parts":[[2018]]}}}