{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,10]],"date-time":"2024-09-10T14:11:56Z","timestamp":1725977516812},"publisher-location":"Cham","reference-count":33,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783319750576"},{"type":"electronic","value":"9783319750583"}],"license":[{"start":{"date-parts":[[2018,1,1]],"date-time":"2018-01-01T00:00:00Z","timestamp":1514764800000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018]]},"DOI":"10.1007\/978-3-319-75058-3_9","type":"book-chapter","created":{"date-parts":[[2018,5,10]],"date-time":"2018-05-10T15:15:04Z","timestamp":1525965304000},"page":"121-133","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["Keeping up with Real Time"],"prefix":"10.1007","author":[{"given":"Reinhard","family":"Wilhelm","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jan","family":"Reineke","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Simon","family":"Wegener","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2018,5,11]]},"reference":[{"key":"9_CR1","doi-asserted-by":"publisher","unstructured":"A.C. Shaw, Reasoning about time in higher-level language software. IEEE Trans. Softw. Eng. 15(7), 875\u2013889 (1989). https:\/\/doi.org\/10.1109\/32.29487","DOI":"10.1109\/32.29487"},{"key":"9_CR2","doi-asserted-by":"crossref","unstructured":"C. Ferdinand, R. Heckmann, M. Langenbach, F. Martin, M. Schmidt, H. Theiling, S. Thesing, R. Wilhelm. Reliable and precise WCET determination for a real-life processor, in EMSOFT, vol. 2211, LNCS 2001, pp. 469\u2013485","DOI":"10.1007\/3-540-45449-7_32"},{"key":"9_CR3","unstructured":"R. Wilhelm, B. Wachter. Abstract interpretation with applications to timing validation, in 20th International Conference on Computer Aided Verification, CAV 2008, Princeton, NJ, USA, 7\u201314 July 2008, Proceedings ed. by A. Gupta, S. Malik. Lecture Notes in Computer Science, vol. 5123 (Springer, Berlin, 2008), pp. 22\u201336. ISBN: 978-3-540-70543-7"},{"key":"9_CR4","doi-asserted-by":"publisher","unstructured":"A. Abel, F. Benz, J. Doerfert, B. D\u00f6rr, S. Hahn, F. Haupenthal, M. Jacobs, A.H. Moin, J. Reineke, B. Schommer, R.Wilhelm, Impact of resource sharing on performance and performance prediction: a survey, in CONCUR 2013 - Concurrency Theory - 24th International Conference, CONCUR 2013, Buenos Aires, Argentina, 27\u201330 August 2013, Proceedings. ed. by P.R. D\u2019Argenio, H.C. Melgratti. Lecture Notes in Computer Science, vol. 8052 (Springer, Berlin, 2013), pp. 25\u201343, ISBN: 978-3-642-40183-1. https:\/\/doi.org\/10.1007\/978-3-642-40184-8","DOI":"10.1007\/978-3-642-40184-8"},{"key":"9_CR5","unstructured":"Certification Authorities Software Team (CAST). Position Paper CAST-32A Multi-core Processors, Nov 2016"},{"key":"9_CR6","doi-asserted-by":"crossref","unstructured":"J. Rosen, A. Andrei, P. Eles, Z. Peng, Bus access optimization for predictable implementation of real-time applications on multiprocessor systems-on-chip, in 28th IEEE International Real-Time Systems Symposium 2007, pp. 49\u201360","DOI":"10.1109\/RTSS.2007.24"},{"key":"9_CR7","doi-asserted-by":"publisher","unstructured":"H. Shah, A. Raabe, A, Knoll. Priority division: A high-speed shared memory bus arbitration with bounded latency, in Design, Automation and Test in Europe, DATE 2011, Grenoble, France, 14\u201318 March 2011, pp. 1497\u20131500. https:\/\/doi.org\/10.1109\/DATE.2011.5763319","DOI":"10.1109\/DATE.2011.5763319"},{"key":"9_CR8","doi-asserted-by":"publisher","unstructured":"R. Pellizzoni, E. Betti, S. Bak, G. Yao, J. Criswell, M. Caccamo, R. Kegley, A predictable execution model for COTS-based embedded systems, in Proceedings of the 17th IEEE Real-Time and Embedded Technology and Applications Symposium (IEEE Computer Society, Washington, DC, USA 2011), pp. 269\u2013279. ISBN: 978-0-7695-4344-4. https:\/\/doi.org\/10.1109\/RTAS.2011.33","DOI":"10.1109\/RTAS.2011.33"},{"key":"9_CR9","doi-asserted-by":"crossref","unstructured":"F. Boniol, H. Cass\u00e9, E. Noulard, C. Pagetti, Deterministic execution model on COTS hardware, in ARCS, 2012, pp. 98\u2013110","DOI":"10.1007\/978-3-642-28293-5_9"},{"key":"9_CR10","doi-asserted-by":"publisher","unstructured":"A. Hamann, D. Dasari, S. Kramer, M. Pressler, F. Wurst. Communication centric design in complex automotive embedded systems, in 29th Euromicro Conference on Real-Time Systems (ECRTS 2017), ed. by M. Bertogna, vol. 76. Leibniz International Proceedings in Informatics (LIPIcs). Dagstuhl, Germany: Schloss Dagstuhl-Leibniz-Zentrum fuer Informatik, 2017, 10:1\u201310:20. ISBN: 978-3-95977-037-8. https:\/\/doi.org\/10.4230\/LIPIcs.ECRTS.2017.10 . http:\/\/drops.dagstuhl.de\/opus\/volltexte\/2017\/7162","DOI":"10.4230\/LIPIcs.ECRTS.2017.10"},{"key":"9_CR11","doi-asserted-by":"crossref","unstructured":"P. Radojkovi\u0107, S. Girbal, A. Grasset, E. Qui\u00f1ones, S. Yehia, F.J. Cazorla, On the evaluation of the impact of shared resources in multithreaded COTS processors in time-critical environments, ACM Trans. Archit. Code Optim. (2012)","DOI":"10.1145\/2086696.2086713"},{"key":"9_CR12","doi-asserted-by":"publisher","unstructured":"Y. Xie, G.H. Loh, PIPP: promotion\/insertion pseudo-partitioning of multi-core shared caches, in Proceedings of the 36th Annual International Symposium on Computer Architecture. ISCA \u201909 (ACM, Austin, TX, USA, 2009), pp. 174\u2013183, ISBN: 978-1-60558-526-0. https:\/\/doi.org\/10.1145\/1555754.1555778","DOI":"10.1145\/1555754.1555778"},{"key":"9_CR13","doi-asserted-by":"publisher","unstructured":"K.J. Nesbit, J. Laudon, J.E. Smith, Virtual private caches, SIGARCH Comput. Archit. News 35(2), 57\u201368 (2007), ISSN: 0163-5964. https:\/\/doi.org\/10.1145\/1273440.1250671","DOI":"10.1145\/1273440.1250671"},{"key":"9_CR14","doi-asserted-by":"crossref","unstructured":"M.K. Qureshi, Y.N. Patt, Utility-based cache partitioning: a low- overhead, high-performance, runtime mechanism to partition shared caches, in IEEE\/ACM International Symposium on Micro Architecture MICRO \u201906 (IEEE Computer Society, 2006), pp. 423\u2013432","DOI":"10.1109\/MICRO.2006.49"},{"key":"9_CR15","doi-asserted-by":"publisher","unstructured":"X. Zhang, S. Dwarkadas, K. Shen, Towards practical page coloring-based multicore cache management, in Proceedings of the 4th ACM European Conference on Computer systems. EuroSys \u201909. Nuremberg, (ACM, Germany, 2009), pp. 89\u2013102, ISBN: 978-1-60558-482-9. https:\/\/doi.org\/10.1145\/1519065.1519076","DOI":"10.1145\/1519065.1519076"},{"key":"9_CR16","doi-asserted-by":"publisher","unstructured":"V. Suhendra, T. Mitra, Exploring locking & partitioning for predictable shared caches on multi-cores, in Proceedings of the 45th Annual Design Automation Conference. DAC \u201908. Anaheim, (ACM, California 2008), pp. 300\u2013303, ISBN: 978-1-60558-115-6. https:\/\/doi.org\/10.1145\/1391469.1391545","DOI":"10.1145\/1391469.1391545"},{"key":"9_CR17","doi-asserted-by":"publisher","unstructured":"G. Taylor, P. Davies, M. Farmwald, The TLB slice - a low-cost highspeed address translation mechanism. SIGARCH Comput. Archit. News 18.3a 355\u2013363 (1990), ISSN: 0163-5964. https:\/\/doi.org\/10.1145\/325096.325161","DOI":"10.1145\/325096.325161"},{"key":"9_CR18","doi-asserted-by":"publisher","unstructured":"J. Reineke, I. Liu, H.D. Patel, S. Kim, E.A. Lee, PRET DRAM controller: bank privatization for predictability and temporal isolation, in Proceedings of the Seventh IEEE\/ACM\/IFIP International Conference On Hardware\/ Software Co design And System Synthesis. CODES+ISSS \u201911. (ACM, Taipei, Taiwan, 2011), pp. 99\u2013108, ISBN: 978-1-4503-0715-4. https:\/\/doi.org\/10.1145\/2039370.2039388","DOI":"10.1145\/2039370.2039388"},{"key":"9_CR19","doi-asserted-by":"crossref","unstructured":"H. Yun, R. Mancuso, Z.-P. Wu, R. Pellizzoni, PALLOC: DRAM bank- aware memory allocator for performance isolation on multicore platforms, in Proceedings of Real-Time and Embedded Technology and Application Symp (RTAS), Berlin, Germany, Apr 2014","DOI":"10.1109\/RTAS.2014.6925999"},{"key":"9_CR20","doi-asserted-by":"publisher","unstructured":"B.D. de Dinechin, D. van Amstel, M. Poulhi\u2018es, G. Lager, Time-critical computing on a single-chip massively parallel processor, in Design, Automation and Test in Europe Conference & Exhibition, DATE 2014, Dresden, Germany, 24-28 March 2014. ed. by G. Fettweis, W. Nebel (European Design and Automation Association, 2014), pp. 1\u20136, ISBN: 978-3-9815370- 2-4. https:\/\/doi.org\/10.7873\/DATE.2014.110","DOI":"10.7873\/DATE.2014.110"},{"key":"9_CR21","doi-asserted-by":"publisher","unstructured":"H. Rihani, M. Moy, C. Maiza, R. I. Davis, S. Altmeyer, Response time analysis of synchronous data flow programs on a many-core processor, in Proceedings of the 24th International Conference on Real-Time Networks and Systems, RTNS 2016, Brest, France, 19\u201321 Oct 2016, pp. 67\u201376. https:\/\/doi.org\/10.1145\/2997465.2997472","DOI":"10.1145\/2997465.2997472"},{"key":"9_CR22","doi-asserted-by":"publisher","unstructured":"A. Gustavsson, A. Ermedahl, B. Lisper, P. Pettersson, Towards WCET analysis of multicore architectures using UPPAAL, in WCET, ed. By B. Lisper, vol. 15. Dagstuhl, Germany, 2010, pp. 101\u2013112, ISBN: 978-3- 939897-21-7. https:\/\/doi.org\/10.4230\/OASIcs.WCET.2010.101","DOI":"10.4230\/OASIcs.WCET.2010.101"},{"key":"9_CR23","doi-asserted-by":"crossref","unstructured":"T. Kelter, P. Marwedel. Parallelism analysis: precise WCET values for complex multi-core systems, in Formal Techniques for Safety-Critical Systems - Third International Workshop, 2014, pp. 142\u2013158","DOI":"10.1007\/978-3-319-17581-2_10"},{"key":"9_CR24","doi-asserted-by":"crossref","unstructured":"T. Kelter, WCET Analysis and Optimization for Multi-Core Real-Time Systems, PhD thesis, TU Dortmund University, 2015","DOI":"10.1109\/SAMOS.2014.6893196"},{"key":"9_CR25","doi-asserted-by":"crossref","unstructured":"S. Schliecker, R. Ernst, Real-time performance analysis of multiprocessor systems with shared memory, ACM Trans. Embed. Comput. Syst. 10(2), 22:1\u201322:27 (2011)","DOI":"10.1145\/1880050.1880058"},{"key":"9_CR26","doi-asserted-by":"publisher","unstructured":"S. Altmeyer, R.I. Davis, L.S. Indrusiak, C. Maiza, V. N\u00e9lis, J. Reineke, A generic and compositional framework for multicore response time analysis, in RTNS, pp. 129\u2013138 (2015). https:\/\/doi.org\/10.1145\/2834848.2834862","DOI":"10.1145\/2834848.2834862"},{"key":"9_CR27","doi-asserted-by":"crossref","unstructured":"W.-H. Huang, J.-J. Chen, J. Reineke, MIRROR: symmetric timing analysis for real-time tasks on multicore platforms with shared resources, in DAC, June 2016","DOI":"10.1145\/2897937.2898046"},{"key":"9_CR28","unstructured":"G.C. Buttazzo, Hard Real-Time Computing Systems: Predictable Scheduling Algorithms and Applications, vol. 23, 2nd edn. (Springer, Real-Time Systems Series, 2004), ISBN 978-0-387-23137-2"},{"key":"9_CR29","doi-asserted-by":"publisher","unstructured":"S. Hahn, M. Jacobs, J. Reineke, Enabling compositionality for multicore timing analysis, in Proceedings of the 24th International Conference on Real Time and Networks Systems (2016). https:\/\/doi.org\/10.1145\/2997465.2997471 , http:\/\/embedded.cs.uni-saarland.de\/publications\/EnablingCompositionalityRTNS2016.pdf","DOI":"10.1145\/2997465.2997471"},{"key":"9_CR30","doi-asserted-by":"publisher","unstructured":"T. Lundqvist, P. Stenstr\u00f6m, Timing anomalies in dynamically scheduled microprocessors, in RTSS, 1999, pp. 12\u201321. https:\/\/doi.org\/10.1109\/REAL.1999.818824","DOI":"10.1109\/REAL.1999.818824"},{"key":"9_CR31","doi-asserted-by":"crossref","unstructured":"S. Hahn, J. Reineke, R. Wilhelm, Toward compact abstractions for processor pipelines, in Correct System Design - Symposium in Honor of Ernst-R\u00fcdiger Olderog on the Occasion of His 60th Birthday, Proceedings. ed. by R. Meyer, A. Platzer, H. Wehrheim, Oldenburg, Germany, 8\u20139 September 2015, pp. 205\u2013220","DOI":"10.1007\/978-3-319-23506-6_14"},{"key":"9_CR32","unstructured":"Infineon Technologies AG. AURIX TC27x D-Step 32-Bit Single-Chip Microcontroller User\u2019s Manual V2.2 2014\u201312 (2014)"},{"key":"9_CR33","doi-asserted-by":"publisher","unstructured":"R. Wilhelm, D. Grund, J. Reineke, M. Schlickling, M. Pister, C. Ferdinand. Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems, IEEE Trans. CAD Integr. Circuits Syst. 28(7) 966\u2013978 (2009). https:\/\/doi.org\/10.1109\/TCAD.2009.2013287","DOI":"10.1109\/TCAD.2009.2013287"}],"container-title":["Advances in Aeronautical Informatics"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-319-75058-3_9","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,10,17]],"date-time":"2019-10-17T21:45:28Z","timestamp":1571348728000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-319-75058-3_9"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018]]},"ISBN":["9783319750576","9783319750583"],"references-count":33,"URL":"https:\/\/doi.org\/10.1007\/978-3-319-75058-3_9","relation":{},"subject":[],"published":{"date-parts":[[2018]]}}}