{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,27]],"date-time":"2025-03-27T16:33:46Z","timestamp":1743093226857,"version":"3.40.3"},"publisher-location":"Cham","reference-count":28,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783319751771"},{"type":"electronic","value":"9783319751788"}],"license":[{"start":{"date-parts":[[2018,1,1]],"date-time":"2018-01-01T00:00:00Z","timestamp":1514764800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2018,1,1]],"date-time":"2018-01-01T00:00:00Z","timestamp":1514764800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018]]},"DOI":"10.1007\/978-3-319-75178-8_53","type":"book-chapter","created":{"date-parts":[[2018,2,7]],"date-time":"2018-02-07T07:12:27Z","timestamp":1517987547000},"page":"664-675","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":3,"title":["Evaluation of a Floating-Point Intensive Kernel on FPGA"],"prefix":"10.1007","author":[{"given":"Zheming","family":"Jin","sequence":"first","affiliation":[]},{"given":"Hal","family":"Finkel","sequence":"additional","affiliation":[]},{"given":"Kazutomo","family":"Yoshii","sequence":"additional","affiliation":[]},{"given":"Franck","family":"Cappello","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2018,2,8]]},"reference":[{"key":"53_CR1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-26408-0","volume-title":"FPGAs for Software Programmers","year":"2016","unstructured":"Koch, D., Hannig, F., Ziener, D. (eds.): FPGAs for Software Programmers. Springer, Cham (2016). https:\/\/doi.org\/10.1007\/978-3-319-26408-0"},{"key":"53_CR2","unstructured":"Intel FPGA SDK for OpenCL Cyclone V SoC Getting Started Guide. Intel (2017)"},{"key":"53_CR3","unstructured":"Intel FPGA SDK for OpenCL Stratix V Network Reference Platform Porting Guide. Intel (2017)"},{"key":"53_CR4","unstructured":"Intel FPGA SDK for OpenCL Arria 10 GX FPGA Development Kit Reference Platform Porting Guide. Intel (2017)"},{"key":"53_CR5","unstructured":"Wirbel, L.: Xilinx SDAccel Whitepaper. Xilinx (2014)"},{"key":"53_CR6","doi-asserted-by":"crossref","unstructured":"Chen, D., Singh, D.: Fractal video compression in OpenCL: an evaluation of CPUs, GPUs, and FPGAs as acceleration platforms. In: Proceedings of 18th Asia and South Pacific Design Automation Conference, pp. 297\u2013304 (2013)","DOI":"10.1109\/ASPDAC.2013.6509612"},{"key":"53_CR7","doi-asserted-by":"crossref","unstructured":"Fifield, J., et al.: Optimizing OpenCL applications on Xilinx FPGA. In: Proceedings of 4th International Workshop on OpenCL. ACM, New York (2016)","DOI":"10.1145\/2909437.2909447"},{"key":"53_CR8","doi-asserted-by":"crossref","unstructured":"Zohouri, H.R., et al.: Evaluating and optimizing OpenCL kernels for high performance computing with FPGAs. In: International Conference for High Performance Computing, Networking, Storage and Analysis, Salt Lake City, UT, pp. 409\u2013420 (2016)","DOI":"10.1109\/SC.2016.34"},{"key":"53_CR9","doi-asserted-by":"crossref","unstructured":"Inggs, G., et al.: Is high level synthesis ready for business? A computational finance case study. In: 2014 International Conference on Field-Programmable Technology (FPT), Shanghai, pp. 12\u201319 (2014)","DOI":"10.1109\/FPT.2014.7082747"},{"key":"53_CR10","doi-asserted-by":"crossref","unstructured":"Underwood, K.: FPGAs vs. CPUs: trends in peak floating-point performance. In: Proceedings of 12th ACM International Symposium on Field-Programmable Gate Arrays, pp. 171\u2013180. ACM Press (2004)","DOI":"10.1145\/968280.968305"},{"key":"53_CR11","doi-asserted-by":"crossref","unstructured":"V\u00e9stias, M., Neto, H.: Trends of CPU GPU and FPGA for high-performance computing. In: 2014 24th International Conference on Field Programmable Logic and Applications, pp. 1\u20136 (2014)","DOI":"10.1109\/FPL.2014.6927483"},{"key":"53_CR12","unstructured":"Govindu, G., et al.: Area and power performance analysis of floating-point-based application on FPGAs. In: Proceedings of 7th Annual Workshop High-Performance Embedded Computing, USA (2003)"},{"key":"53_CR13","doi-asserted-by":"crossref","unstructured":"Che, S., et al.: Accelerating compute-intensive applications with GPUs and FPGAs. In: Symposium on Application Specific Processors, USA, pp. 101\u2013107 (2008)","DOI":"10.1109\/SASP.2008.4570793"},{"key":"53_CR14","doi-asserted-by":"crossref","unstructured":"Ndu, G., et al.: CHO: towards a benchmark suite for OpenCL FPGA accelerators. In: 3rd IWOCL International Workshop on OpenCL, California, USA (2015)","DOI":"10.1145\/2791321.2791331"},{"key":"53_CR15","unstructured":"Taking Advantage of Advances in FPGA Floating-Point IP Cores. Altera (2009)"},{"key":"53_CR16","unstructured":"Enabling High-Performance Floating-Point Designs. Intel (2016)"},{"key":"53_CR17","doi-asserted-by":"crossref","unstructured":"Jin, Z., et al.: Evaluation of CHO benchmarks on the Arria 10 FPGA using the Intel FPGA SDK for OpenCL. Argonne Leadership Computing Facility, Argonne National Laboratory, ANL\/ALCF-17\/4 (2017)","DOI":"10.2172\/1372106"},{"key":"53_CR18","unstructured":"Leeser, M., et al.: OpenCL floating point software on heterogeneous architectures\u2013portable or not. In: Workshop on Numerical Software Verification (NSV) (2012)"},{"key":"53_CR19","unstructured":"Wikipedia Webpage: https:\/\/en.wikipedia.org\/wiki\/Geographical_distance"},{"key":"53_CR20","unstructured":"GpsDrive Homepage: http:\/\/www.gpsdrive.de\/"},{"key":"53_CR21","unstructured":"Geographiclib Homepage: https:\/\/geographiclib.sourceforge.io\/2009-03\/geodesic.html"},{"key":"53_CR22","unstructured":"Intel FPGA SDK for OpenCL Programming Guide. UG-OCL002. Intel (2016)"},{"key":"53_CR23","unstructured":"Arria 10 Native Floating-Point DSP IP Core User Guide. Intel (2016)"},{"key":"53_CR24","volume-title":"Intel Xeon Phi Processor High Performance Programming: Knights Landing Edition","author":"J Jeffers","year":"2016","unstructured":"Jeffers, J., et al.: Intel Xeon Phi Processor High Performance Programming: Knights Landing Edition. Morgan Kaufmann Publishers, San Francisco (2016)"},{"key":"53_CR25","unstructured":"Maxmind Database Homepage: https:\/\/www.maxmind.com\/en\/free-world-cities-database"},{"key":"53_CR26","unstructured":"CUDA C Programming Guide. NVIDIA (2017)"},{"key":"53_CR27","unstructured":"Leveraging the Intel HyperFlex FPGA Architecture in Intel Stratix 10 Devices to Achieve Maximum Power Reduction. Intel (2016)"},{"key":"53_CR28","unstructured":"Stratix 10 GX\/SX Device Overview. Intel (2016)"}],"container-title":["Lecture Notes in Computer Science","Euro-Par 2017: Parallel Processing Workshops"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-319-75178-8_53","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,2,8]],"date-time":"2022-02-08T01:08:22Z","timestamp":1644282502000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-319-75178-8_53"}},"subtitle":["A Case Study of Geodesic Distance Kernel"],"short-title":[],"issued":{"date-parts":[[2018]]},"ISBN":["9783319751771","9783319751788"],"references-count":28,"URL":"https:\/\/doi.org\/10.1007\/978-3-319-75178-8_53","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2018]]},"assertion":[{"value":"8 February 2018","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"Euro-Par","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"European Conference on Parallel Processing","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Santiago de Compostela","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Spain","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2017","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"28 August 2017","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"1 September 2017","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"23","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"europar2017","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"http:\/\/europar2017.usc.es","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"This content has been made available to all.","name":"free","label":"Free to read"}]}}