{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,10]],"date-time":"2024-09-10T12:09:37Z","timestamp":1725970177277},"publisher-location":"Cham","reference-count":19,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783319776095"},{"type":"electronic","value":"9783319776101"}],"license":[{"start":{"date-parts":[[2018,1,1]],"date-time":"2018-01-01T00:00:00Z","timestamp":1514764800000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018]]},"DOI":"10.1007\/978-3-319-77610-1_13","type":"book-chapter","created":{"date-parts":[[2018,3,7]],"date-time":"2018-03-07T02:32:50Z","timestamp":1520389970000},"page":"168-180","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":2,"title":["Improving the Performance of STT-MRAM LLC Through Enhanced Cache Replacement Policy"],"prefix":"10.1007","author":[{"given":"Pierre-Yves","family":"P\u00e9neau","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"David","family":"Novo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Florent","family":"Bruguier","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lionel","family":"Torres","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gilles","family":"Sassatelli","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Abdoulaye","family":"Gamati\u00e9","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2018,3,8]]},"reference":[{"key":"13_CR1","unstructured":"The ChampSim simulator. https:\/\/github.com\/ChampSim\/ChampSim"},{"key":"13_CR2","unstructured":"DDR3-Micron MT41K512M8DA-125 datasheet, October 2017. https:\/\/www.micron.com\/~\/media\/documents\/products\/data-sheet\/dram\/ddr3\/4gb_ddr3l.pdf"},{"key":"13_CR3","unstructured":"ISCA 2017 Cache Replacement Championship. http:\/\/crc2.ece.tamu.edu"},{"key":"13_CR4","unstructured":"International Technology Roadmap for Semiconductors (ITRS) (2015)"},{"issue":"2","key":"13_CR5","doi-asserted-by":"crossref","first-page":"78","DOI":"10.1147\/sj.52.0078","volume":"5","author":"LA Belady","year":"1966","unstructured":"Belady, L.A.: A study of replacement algorithms for a virtual-storage computer. IBM Syst. J. 5(2), 78\u2013101 (1966)","journal-title":"IBM Syst. J."},{"issue":"7","key":"13_CR6","doi-asserted-by":"crossref","first-page":"994","DOI":"10.1109\/TCAD.2012.2185930","volume":"31","author":"X Dong","year":"2012","unstructured":"Dong, X., Xu, C., Xie, Y., Jouppi, N.P.: NVSim: a circuit-level performance, energy, and area model for emerging nonvolatile memory. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 31(7), 994\u20131007 (2012)","journal-title":"IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst."},{"issue":"4","key":"13_CR7","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/1186736.1186737","volume":"34","author":"JL Henning","year":"2006","unstructured":"Henning, J.L.: SPEC CPU2006 benchmark descriptions. ACM SIGARCH Comput. Archit. News 34(4), 1\u201317 (2006)","journal-title":"ACM SIGARCH Comput. Archit. News"},{"key":"13_CR8","doi-asserted-by":"crossref","unstructured":"Jain, A., Lin, C.: Back to the future: leveraging Belady\u2019s algorithm for improved cache replacement. In: 2016 ACM\/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA), pp. 78\u201389. IEEE (2016)","DOI":"10.1109\/ISCA.2016.17"},{"key":"13_CR9","unstructured":"Kommaraju, A.V.: Designing energy-aware optimization techniques through program behavior analysis. Ph.D. thesis, Indian Institute of Science, Bangalore (2014)"},{"key":"13_CR10","doi-asserted-by":"crossref","unstructured":"Li, Q., Shi, L., Li, J., Xue, C.J., He, Y.: Code motion for migration minimization in STT-RAM based hybrid cache. In: 2012 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 410\u2013415. IEEE (2012)","DOI":"10.1109\/ISVLSI.2012.84"},{"issue":"1","key":"13_CR11","first-page":"33","volume":"4","author":"S Mittal","year":"2014","unstructured":"Mittal, S.: A survey of architectural techniques for improving cache power efficiency. Sustain. Comput.: Inform. Syst. 4(1), 33\u201343 (2014)","journal-title":"Sustain. Comput.: Inform. Syst."},{"key":"13_CR12","unstructured":"Muralimanohar, N., Balasubramonian, R., Jouppi, N.P.: CACTI 6.0: a tool to model large caches. HP Laboratories, pp. 22\u201331 (2009)"},{"key":"13_CR13","doi-asserted-by":"crossref","unstructured":"P\u00e9neau, P.Y., Bouziane, R., Gamati\u00e9, A., Rohou, E., Bruguier, F., Sassatelli, G., Torres, L., Senni, S.: Loop optimization in presence of STT-MRAM caches: a study of performance-energy tradeoffs. In: 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), pp. 162\u2013169. IEEE (2016)","DOI":"10.1109\/PATMOS.2016.7833682"},{"key":"13_CR14","doi-asserted-by":"crossref","unstructured":"Senni, S., Delobelle, T., Coi, O., P\u00e9neau, P.Y., Torres, L., Gamati\u00e9, A., Benoit, P., Sassatelli, G.: Embedded systems to high performance computing using STT-MRAM. In: 2017 Design, Automation and Test in Europe Conference and Exhibition (DATE), pp. 536\u2013541. IEEE (2017)","DOI":"10.23919\/DATE.2017.7927046"},{"key":"13_CR15","doi-asserted-by":"crossref","unstructured":"Smullen, C.W., Mohan, V., Nigam, A., Gurumurthi, S., Stan, M.R.: Relaxing non-volatility for fast and energy-efficient STT-RAM caches. In: 2011 IEEE 17th International Symposium on High Performance Computer Architecture (HPCA), pp. 50\u201361. IEEE (2011)","DOI":"10.1109\/HPCA.2011.5749716"},{"key":"13_CR16","doi-asserted-by":"crossref","unstructured":"Sun, G., Dong, X., Xie, Y., Li, J., Chen, Y.: A novel architecture of the 3D stacked MRAM L2 cache for CMPs. In: IEEE 15th International Symposium on High Performance Computer Architecture, HPCA 2009, pp. 239\u2013249. IEEE (2009)","DOI":"10.1109\/HPCA.2009.4798259"},{"issue":"2","key":"13_CR17","doi-asserted-by":"crossref","first-page":"73","DOI":"10.1109\/MCSE.2015.4","volume":"17","author":"JS Vetter","year":"2015","unstructured":"Vetter, J.S., Mittal, S.: Opportunities for nonvolatile memory systems in extreme-scale high-performance computing. Comput. Sci. Eng. 17(2), 73\u201382 (2015)","journal-title":"Comput. Sci. Eng."},{"key":"13_CR18","doi-asserted-by":"crossref","unstructured":"Wu, X., Li, J., Zhang, L., Speight, E., Rajamony, R., Xie, Y.: Hybrid cache architecture with disparate memory technologies. In: ACM SIGARCH Computer Architecture News, vol. 37, pp. 34\u201345. ACM (2009)","DOI":"10.1145\/1555754.1555761"},{"key":"13_CR19","doi-asserted-by":"crossref","unstructured":"Zhou, P., Zhao, B., Yang, J., Zhang, Y.: Energy reduction for STT-RAM using early write termination. In: IEEE\/ACM International Conference on Computer-Aided Design-Digest of Technical Papers, ICCAD 2009, pp. 264\u2013268. IEEE (2009)","DOI":"10.1145\/1687399.1687448"}],"container-title":["Lecture Notes in Computer Science","Architecture of Computing Systems \u2013 ARCS 2018"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-319-77610-1_13","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,10,12]],"date-time":"2019-10-12T05:39:42Z","timestamp":1570858782000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-319-77610-1_13"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018]]},"ISBN":["9783319776095","9783319776101"],"references-count":19,"URL":"https:\/\/doi.org\/10.1007\/978-3-319-77610-1_13","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2018]]}}}