{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,8]],"date-time":"2025-10-08T16:42:40Z","timestamp":1759941760678,"version":"3.40.3"},"publisher-location":"Cham","reference-count":22,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783319788890"},{"type":"electronic","value":"9783319788906"}],"license":[{"start":{"date-parts":[[2018,1,1]],"date-time":"2018-01-01T00:00:00Z","timestamp":1514764800000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018]]},"DOI":"10.1007\/978-3-319-78890-6_28","type":"book-chapter","created":{"date-parts":[[2018,4,7]],"date-time":"2018-04-07T04:52:40Z","timestamp":1523076760000},"page":"343-354","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":4,"title":["Runtime Adaptive Cache for the LEON3 Processor"],"prefix":"10.1007","author":[{"given":"Osvaldo","family":"Navarro","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael","family":"Huebner","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2018,4,8]]},"reference":[{"issue":"1","key":"28_CR1","first-page":"33","volume":"4","author":"S Mittal","year":"2014","unstructured":"Mittal, S.: A survey of architectural techniques for improving cache power efficiency. Sustain. Comput. Inf. Syst. 4(1), 33\u201343 (2014)","journal-title":"Sustain. Comput. Inf. Syst."},{"key":"28_CR2","volume-title":"Computer Architecture: A Quantitative Approach","author":"JL Hennessy","year":"2011","unstructured":"Hennessy, J.L., Patterson, D.A.: Computer Architecture: A Quantitative Approach. Elsevier, Amsterdam (2011)"},{"key":"28_CR3","doi-asserted-by":"publisher","unstructured":"Silva, B.A., Cuminato, L.A., Bonato, V., Diniz, P.C.: Run-time cache configuration for the LEON-3 embedded processor. In: Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, SBCCI 2015, pp. 42:1\u201342:6. ACM, New York (2015). https:\/\/doi.org\/10.1145\/2800986.2801026","DOI":"10.1145\/2800986.2801026"},{"key":"28_CR4","unstructured":"LEON3\u2019s download webpage. grlib-gpl-2017.2-b4164.tar.gz, August 2017. http:\/\/www.gaisler.com\/index.php\/downloads\/leongrlib"},{"key":"28_CR5","doi-asserted-by":"crossref","unstructured":"Albonesi, D.H.: Selective cache ways: on-demand cache resource allocation. In: 1999 Proceedings of 32nd Annual International Symposium on Microarchitecture, MICRO-32, pp. 248\u2013259. IEEE (1999)","DOI":"10.1109\/MICRO.1999.809463"},{"key":"28_CR6","doi-asserted-by":"crossref","unstructured":"Zhang, C., Vahid, F., Najjar, W.: A highly configurable cache architecture for embedded systems. In: 2003 Proceedings of 30th Annual International Symposium on Computer Architecture, pp. 136\u2013146. IEEE (2003)","DOI":"10.1145\/859618.859635"},{"key":"28_CR7","doi-asserted-by":"crossref","unstructured":"Gupta, S., Gao, H., Zhou, H.: Adaptive cache bypassing for inclusive last levelcaches. In: 2013 IEEE 27th International Symposium on Parallel and Distributed Processing (IPDPS), pp. 1243\u20131253. IEEE (2013)","DOI":"10.1109\/IPDPS.2013.16"},{"issue":"8","key":"28_CR8","doi-asserted-by":"publisher","first-page":"1653","DOI":"10.1109\/TVLSI.2013.2278289","volume":"22","author":"S Mittal","year":"2014","unstructured":"Mittal, S., Cao, Y., Zhang, Z.: Master: a multicore cache energy-saving technique using dynamic cache reconfiguration. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 22(8), 1653\u20131665 (2014)","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"issue":"1","key":"28_CR9","doi-asserted-by":"publisher","first-page":"80","DOI":"10.1109\/TVLSI.2008.2002459","volume":"17","author":"A Gordon-Ross","year":"2009","unstructured":"Gordon-Ross, A., Vahid, F., Dutt, N.D.: Fast configurable-cache tuning with a unified second-level cache. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 17(1), 80\u201391 (2009)","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"issue":"2","key":"28_CR10","first-page":"28","volume":"11","author":"W Wang","year":"2012","unstructured":"Wang, W., Mishra, P., Gordon-Ross, A.: Dynamic cache reconfiguration for soft real-time systems. ACM Trans. Embed. Comput. Syst. (TECS) 11(2), 28 (2012)","journal-title":"ACM Trans. Embed. Comput. Syst. (TECS)"},{"key":"28_CR11","doi-asserted-by":"crossref","unstructured":"Navarro, O., H\u00fcbner, M.: An adaptive victim cache scheme. In: 2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig), pp. 1\u20134. IEEE (2014)","DOI":"10.1109\/ReConFig.2014.7032496"},{"key":"28_CR12","doi-asserted-by":"crossref","unstructured":"Navarro, O., Leiding, T., H\u00fcbner, M.: Configurable cache tuning with a victim cache. In: 2015 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), pp. 1\u20136. IEEE (2015)","DOI":"10.1109\/ReCoSoC.2015.7238080"},{"key":"28_CR13","doi-asserted-by":"crossref","unstructured":"Navarro, O., Leiding, T., H\u00fcbner, M.: A dynamic cache reconfiguration platform for soft real-time systems. In: 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 388\u2013391. IEEE (2016)","DOI":"10.1109\/ICECS.2016.7841214"},{"key":"28_CR14","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"311","DOI":"10.1007\/978-3-319-56258-2_27","volume-title":"Applied Reconfigurable Computing","author":"O Navarro","year":"2017","unstructured":"Navarro, O., Mori, J., Hoffmann, J., Stuckmann, F., H\u00fcbner, M.: A machine learning methodology for cache recommendation. In: Wong, S., Beck, A.C., Bertels, K., Carro, L. (eds.) ARC 2017. LNCS, vol. 10216, pp. 311\u2013322. Springer, Cham (2017). https:\/\/doi.org\/10.1007\/978-3-319-56258-2_27"},{"key":"28_CR15","doi-asserted-by":"crossref","unstructured":"Gianelli, S., Adegbija, T.: PACT: priority-aware phase-based cache tuning for embedded systems. In: 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 403\u2013408. IEEE (2017)","DOI":"10.1109\/ISVLSI.2017.77"},{"issue":"4","key":"28_CR16","doi-asserted-by":"publisher","first-page":"874","DOI":"10.1109\/TC.2013.18","volume":"63","author":"D Kaseridis","year":"2014","unstructured":"Kaseridis, D., Iqbal, M.F., John, L.K.: Cache friendliness-aware managementof shared last-level caches for highperformance multi-core systems. IEEE Trans. Comput. 63(4), 874\u2013887 (2014)","journal-title":"IEEE Trans. Comput."},{"issue":"2","key":"28_CR17","doi-asserted-by":"publisher","first-page":"407","DOI":"10.1145\/993396.993405","volume":"3","author":"C Zhang","year":"2004","unstructured":"Zhang, C., Vahid, F., Lysecky, R.: A self-tuning cache architecture for embedded systems. ACM Trans. Embed. Comput. Syst. (TECS) 3(2), 407\u2013425 (2004)","journal-title":"ACM Trans. Embed. Comput. Syst. (TECS)"},{"key":"28_CR18","unstructured":"Xilinx zynq-7000 all programmable soc zc702 evaluation kit\u2019s webpage, August 2017. https:\/\/www.xilinx.com\/products\/boards-and-kits\/ek-z7-zc702-g.html"},{"key":"28_CR19","unstructured":"GRMON2\u2019s webpage, August 2017. http:\/\/www.gaisler.com\/index.php\/downloads\/debug-tools"},{"key":"28_CR20","unstructured":"Fusion digital power designer\u2019s webpage, August 2017. http:\/\/www.ti.com\/tool\/fusion_digital_power_designer"},{"key":"28_CR21","unstructured":"Mibench benchmark suite\u2019s webpage, August 2017. http:\/\/vhosts.eecs.umich.edu\/mibench\/\/"},{"key":"28_CR22","unstructured":"Baseline source files (2017). https:\/\/www.dropbox.com\/sh\/2a73k3j5cxzavxw\/IBz513-Gk6"}],"container-title":["Lecture Notes in Computer Science","Applied Reconfigurable Computing. Architectures, Tools, and Applications"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-319-78890-6_28","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,10,14]],"date-time":"2019-10-14T13:19:44Z","timestamp":1571059184000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-319-78890-6_28"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018]]},"ISBN":["9783319788890","9783319788906"],"references-count":22,"URL":"https:\/\/doi.org\/10.1007\/978-3-319-78890-6_28","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2018]]}}}