{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,27]],"date-time":"2025-03-27T17:44:22Z","timestamp":1743097462652,"version":"3.40.3"},"publisher-location":"Cham","reference-count":26,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783319788890"},{"type":"electronic","value":"9783319788906"}],"license":[{"start":{"date-parts":[[2018,1,1]],"date-time":"2018-01-01T00:00:00Z","timestamp":1514764800000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018]]},"DOI":"10.1007\/978-3-319-78890-6_35","type":"book-chapter","created":{"date-parts":[[2018,4,7]],"date-time":"2018-04-07T04:52:40Z","timestamp":1523076760000},"page":"433-445","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":3,"title":["An Intrusive Dynamic Reconfigurable Cycle-Accurate Debugging System for Embedded Processors"],"prefix":"10.1007","author":[{"given":"Habib ul Hasan","family":"Khan","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ahmed","family":"Kamal","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Diana","family":"Goehringer","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2018,4,8]]},"reference":[{"key":"35_CR1","unstructured":"Khan, H., G\u00f6hringer, D.: FPGA debugging by a device start and stop approach. In: IEEE International Conference on ReConFigurable Computing and FPGAs (ReConFig) (2016)"},{"key":"35_CR2","doi-asserted-by":"crossref","unstructured":"Abramovici, M., Bradley, P., Dwarakanath, K.: A reconfigurable design-for-debug infrastructure for SoCs. In: 2006 43rd ACM\/IEEE Design Automation Conference (2006)","DOI":"10.1109\/DAC.2006.238683"},{"key":"35_CR3","unstructured":"Herrmann, A., Nugent, G.: Embedded logic analyzer for a programmable logic device. U.S. Patent No. 6,389,558, 14 May 2002"},{"key":"35_CR4","doi-asserted-by":"crossref","unstructured":"Wrighton, M.G., DeHon, A.M.: Hardware-assisted simulated annealing with application for fast FPGA placement. In: Proceedings of the 2003 ACM\/SIGDA Eleventh International Symposium on Field Programmable Gate Arrays, pp. 33\u201342. ACM (2003)","DOI":"10.1145\/611823.611824"},{"key":"35_CR5","doi-asserted-by":"crossref","unstructured":"Lie, W., Wu, F.-Y.: Dynamic partial reconfiguration in FPGAs. In: Third International Symposium on Intelligent Information Technology Application, IITA 2009, vol. 2. IEEE (2009)","DOI":"10.1109\/IITA.2009.334"},{"key":"35_CR6","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"483","DOI":"10.1007\/3-540-44687-7_50","volume-title":"Field-Programmable Logic and Applications","author":"T Wheeler","year":"2001","unstructured":"Wheeler, T., Graham, P., Nelson, B., Hutchings, B.: Using design-level scan to improve FPGA design observability and controllability for functional verification. In: Brebner, G., Woods, R. (eds.) FPL 2001. LNCS, vol. 2147, pp. 483\u2013492. Springer, Heidelberg (2001). \n                      https:\/\/doi.org\/10.1007\/3-540-44687-7_50"},{"issue":"2","key":"35_CR7","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/2566668","volume":"19","author":"Eddie Hung","year":"2014","unstructured":"Hung, E., Wilton, S.J.E.: Accelerating FPGA debug: increasing visibility using a runtime reconfigurable observation and triggering network. ACM Trans. Des. Autom. Electron. Syst. (TODAES) 19(2), 14 (2014)","journal-title":"ACM Transactions on Design Automation of Electronic Systems"},{"key":"35_CR8","doi-asserted-by":"crossref","unstructured":"Hung, E., Wilton, S.J.E.: Towards simulator-like observability for FPGAs: a virtual overlay network for trace-buffers. In: Proceedings of the ACM\/SIGDA International Symposium on Field Programmable Gate Arrays. ACM (2013)","DOI":"10.1145\/2435264.2435272"},{"key":"35_CR9","doi-asserted-by":"crossref","unstructured":"Iskander, Y., Cameron, D., Patterson, D., Craven, S.D.: Improved abstractions and turnaround time for FPGA design validation and debug. In: 21st International Conference on Field Programmable Logic and Applications. IEEE (2011)","DOI":"10.1109\/FPL.2011.102"},{"key":"35_CR10","doi-asserted-by":"crossref","unstructured":"Chandrasekharan, A., et al.: Accelerating FPGA development through the automatic parallel application of standard implementation tools. In: 2010 International Conference on Field-Programmable Technology (FPT). IEEE (2010)","DOI":"10.1109\/FPT.2010.5681754"},{"key":"35_CR11","unstructured":"Graham, P., Nelson, B., Hutchings, B.: Instrumenting bitstreams for debugging FPGA circuits. In: The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2001. IEEE (2001)"},{"key":"35_CR12","doi-asserted-by":"crossref","unstructured":"Lagadec, L., Picard, D.: Software-like debugging methodology for reconfigurable platforms. In: IEEE International Symposium on Parallel & Distributed Processing, IPDPS 2009. IEEE (2009)","DOI":"10.1109\/IPDPS.2009.5161224"},{"key":"35_CR13","doi-asserted-by":"crossref","unstructured":"Poulos, Z., Yang, Y.S., Anderson, J., Veneris, A., Le, B.: Leveraging reconfigurability to raise productivity in FPGA functional debug. In: Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 292\u2013295. IEEE, March 2012","DOI":"10.1109\/DATE.2012.6176481"},{"key":"35_CR14","doi-asserted-by":"crossref","unstructured":"Abramovici, M., Bradley, P., Dwarakanath, K., Levin, P., Memmi, G., Miller, D.: A reconfigurable design-for-debug infrastructure for SoCs. In: Proceedings of the 43rd Annual Design Automation Conference, pp. 7\u201312. ACM, July 2006","DOI":"10.1109\/DAC.2006.238683"},{"key":"35_CR15","unstructured":"Quinton, B., Wilton, S.: Programmable logic core based post-silicon debug for SoCs. In: 4th IEEE Silicon Debug and Diagnosis Workshop, May 2007"},{"key":"35_CR16","doi-asserted-by":"crossref","unstructured":"Kudlugi, M., Hassoun, S., Selvidge, C., Pryor, D.: A transaction-based unified simulation\/emulation architecture for functional verification. In: Design Automation Conference Proceedings, pp. 623\u2013628. IEEE, June 2001","DOI":"10.1145\/378239.379036"},{"issue":"3","key":"35_CR17","doi-asserted-by":"publisher","first-page":"208","DOI":"10.1109\/MDT.2008.66","volume":"25","author":"Bart Vermeulen","year":"2008","unstructured":"Vermeulen, B.: Functional debug techniques for embedded systems. IEEE Des. Test Comput. 25(3) (2008)","journal-title":"IEEE Design & Test of Computers"},{"key":"35_CR18","doi-asserted-by":"crossref","unstructured":"Panjkov, Z., Wasserbauer, A., Ostermann, T., Hagelauer, R.: Hybrid FPGA debug approach. In: 2015 25th International Conference on Field Programmable Logic and Applications (FPL), pp. 1\u20138. IEEE, September 2015","DOI":"10.1109\/FPL.2015.7294023"},{"key":"35_CR19","unstructured":"https:\/\/www.xilinx.com\/support\/documentation\/sw_manuals\/\u2026\/mb_ref_guide.pdf"},{"key":"35_CR20","unstructured":"http:\/\/www.lauterbach.com"},{"key":"35_CR21","unstructured":"VectorBlox Computing Inc.: VectorBlox\/risc-v. \n                      https:\/\/github.com\/VectorBlox\/risc-v"},{"key":"35_CR22","unstructured":"Ng, H.-C., Liu, C., So, H.K.H.: A soft processor overlay with tightly-coupled FPGA accelerator. arXiv preprint \n                      arXiv:1606.06483\n                      \n                     (2016)"},{"key":"35_CR23","unstructured":"https:\/\/www.xilinx.com\/support\/documentation\/ip_documentation\/clk_wiz\/v5_3\/pg065-clk-wiz.pdf"},{"key":"35_CR24","doi-asserted-by":"crossref","unstructured":"Khan, H., Grimm, T., H\u00fcbner, M., G\u00f6hringer, D.: Access network generation for efficient debugging of FPGAs. In: International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, HEART 2017 (2017)","DOI":"10.1145\/3120895.3120920"},{"key":"35_CR25","unstructured":"Xilinx Inc.: Partial Reconfiguration User Guide UG909 v2017.1 (2017)"},{"key":"35_CR26","doi-asserted-by":"crossref","unstructured":"Kamaleldin, A., Ahmed, I., Obeid, A.M., Shalash, A., Ismail, Y., Mostafa, H.: A cost-effective dynamic partial reconfiguration implementation flow for Xilinx FPGA. In: New Generation CAS (NGCAS) 2017, pp. 281\u2013284. IEEE, September 2017","DOI":"10.1109\/NGCAS.2017.17"}],"container-title":["Lecture Notes in Computer Science","Applied Reconfigurable Computing. Architectures, Tools, and Applications"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-319-78890-6_35","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,20]],"date-time":"2019-05-20T03:37:58Z","timestamp":1558323478000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-319-78890-6_35"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018]]},"ISBN":["9783319788890","9783319788906"],"references-count":26,"URL":"https:\/\/doi.org\/10.1007\/978-3-319-78890-6_35","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2018]]},"assertion":[{"value":"8 April 2018","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"ARC","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"International Symposium on Applied Reconfigurable Computing","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Santorini","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Greece","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2018","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2 May 2018","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"4 May 2018","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"14","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"arc2018","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"http:\/\/arc2018.esda-lab.cied.teiwest.gr\/","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}}]}}