{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,4]],"date-time":"2025-07-04T04:11:38Z","timestamp":1751602298723,"version":"3.41.0"},"publisher-location":"Cham","reference-count":20,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783319900223"},{"type":"electronic","value":"9783319900230"}],"license":[{"start":{"date-parts":[[2017,1,1]],"date-time":"2017-01-01T00:00:00Z","timestamp":1483228800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2017,1,1]],"date-time":"2017-01-01T00:00:00Z","timestamp":1483228800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017]]},"DOI":"10.1007\/978-3-319-90023-0_11","type":"book-chapter","created":{"date-parts":[[2018,4,16]],"date-time":"2018-04-16T12:56:48Z","timestamp":1523883408000},"page":"128-141","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Modeling and Analysis of SLDL-Captured NoC Abstractions"],"prefix":"10.1007","author":[{"given":"Ran","family":"Hao","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nasibeh","family":"Teimouri","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kasra","family":"Moazzemi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gunar","family":"Schirner","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2018,4,17]]},"reference":[{"key":"11_CR1","doi-asserted-by":"crossref","unstructured":"Sgroi, M., Sheets, M., Mihal, A., Keutzer, K., Malik, S., Rabaey, J., Sangiovanni-Vencentelli, A.: Addressing the system-on-a-chip interconnect woes through communication-based design. In: Design Automation Conference (DAC), pp. 667\u2013672. ACM (2001)","DOI":"10.1145\/378239.379045"},{"issue":"5","key":"11_CR2","doi-asserted-by":"publisher","first-page":"96","DOI":"10.1109\/MM.2007.4378787","volume":"27","author":"J Owens","year":"2007","unstructured":"Owens, J., Dally, W., Ho, R., Jayasimha, D.N., Keckler, S., Peh, L.-S.: Research challenges for on-chip interconnection networks. Micro IEEE 27(5), 96\u2013108 (2007)","journal-title":"Micro IEEE"},{"key":"11_CR3","doi-asserted-by":"crossref","unstructured":"Dally, W., Towles, B.: Route packets, not wires: on-chip interconnection networks. In: Design Automation Conference (DAC), pp. 684\u2013689 (2001)","DOI":"10.1145\/378239.379048"},{"key":"11_CR4","doi-asserted-by":"crossref","unstructured":"Moraes, F., Calazans, N., Mello, A., M\u00f6ller, L., Ost, L.: HERMES: an infrastructure for low area overhead packet-switching networks on chip. Integr. VLSI J. 38(1), 69\u201393 (2004)","DOI":"10.1016\/j.vlsi.2004.03.003"},{"key":"11_CR5","doi-asserted-by":"crossref","unstructured":"Foroutan, S., Thonnart, Y., Hersemeule, R., Jerraya, A.: An analytical method for evaluating Network-on-Chip performance. In: Design, Automation Test in Europe (DATE), pp. 1629\u20131632 (2010)","DOI":"10.1109\/DATE.2010.5457072"},{"key":"11_CR6","doi-asserted-by":"publisher","unstructured":"Schirner, G., D\u00f6mer, R.: Abstract communication modeling: a case study using the CAN automotive bus. In: Rettberg, A., Zanella, M.C., Rammig, F.J. (eds.) From Specification to Embedded Systems Application. IFIPAICT, vol. 184, pp. 189\u2013200. Springer, Heidelberg (2005). https:\/\/doi.org\/10.1007\/11523277_19","DOI":"10.1007\/11523277_19"},{"key":"11_CR7","doi-asserted-by":"crossref","unstructured":"Schirner, G., D\u00f6mer, R.: Quantitative analysis of transaction level models for the AMBA bus. In: Design, Automation and Test in Europe (DATE), vol. 1, pp. 1\u20136 (2006)","DOI":"10.1109\/DATE.2006.244108"},{"key":"11_CR8","doi-asserted-by":"crossref","unstructured":"Lu, K., Muller-Gritschneder, D., Schlichtmann, U.: Accurately timed transaction level models for virtual prototyping at high abstraction level. In: Design, Automation Test in Europe Conference Exhibition (DATE), pp. 135\u2013140 (2012)","DOI":"10.1109\/DATE.2012.6176446"},{"key":"11_CR9","doi-asserted-by":"crossref","unstructured":"Indrusiak, L., dos Santos, O.: Fast and accurate transaction-level model of a wormhole network-on-chip with priority preemptive virtual channel arbitration. In: Design, Automation Test in Europe Conference (DATE), pp. 1\u20136 (2011)","DOI":"10.1109\/DATE.2011.5763179"},{"key":"11_CR10","doi-asserted-by":"crossref","unstructured":"Nayebi, A., Meraji, S., Shamaei, A., Sarbazi-Azad, H.: XMulator: a listener-based integrated simulation platform for interconnection networks. In: International Modeling Simulation (AMS), pp. 128\u2013132 (2007)","DOI":"10.1109\/AMS.2007.112"},{"key":"11_CR11","doi-asserted-by":"crossref","unstructured":"Jiang, N., Becker, D., Michelogiannakis, G., Balfour, J., Towles, B., Shaw, D., Kim, J., Dally, W.: A detailed and flexible cycle-accurate network-on-chip simulator. In: IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pp. 86\u201396 (2013)","DOI":"10.1109\/ISPASS.2013.6557149"},{"key":"11_CR12","doi-asserted-by":"crossref","unstructured":"Hosseinabady, M., Nunez-Yanez, J.: SystemC architectural transaction level modelling for large NoCs. In: Forum on Specification Design Languages (FDL), pp. 1\u20136 (2010)","DOI":"10.1049\/ic.2010.0143"},{"key":"11_CR13","doi-asserted-by":"crossref","unstructured":"Viaud, E., Potop-Butucaru, D., Greiner, A.: An efficient TLM\/T modeling and simulation environment based on conservative parallel discrete event principles. In: Design, Automation and Test in Europe (DATE), pp. 1\u20136 (2006)","DOI":"10.1109\/DATE.2006.244003"},{"key":"11_CR14","doi-asserted-by":"crossref","unstructured":"Suboh, S., Bakhouya, M., Gaber, J., El-Ghazawi, T.: Analytical modeling and evaluation of network-on-chip architectures. In: High Performance Computing and Simulation (HPCS), pp. 615\u2013622 (2010)","DOI":"10.1109\/HPCS.2010.5547064"},{"issue":"12","key":"11_CR15","doi-asserted-by":"publisher","first-page":"2001","DOI":"10.1109\/TCAD.2010.2061613","volume":"29","author":"U Ogras","year":"2010","unstructured":"Ogras, U., Bogdan, P., Marculescu, R.: An analytical approach for network-on-chip performance analysis. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 29(12), 2001\u20132013 (2010)","journal-title":"IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."},{"key":"11_CR16","doi-asserted-by":"crossref","unstructured":"van Moll, H., Corporaal, H., Reyes, V., Boonen, M.: Fast and accurate protocol specific bus modeling using TLM 2.0. In: Design, Automation Test in Europe (DATE), pp. 316\u2013319 (2009)","DOI":"10.1109\/DATE.2009.5090680"},{"key":"11_CR17","doi-asserted-by":"publisher","DOI":"10.1007\/b137175","volume-title":"Transaction-Level Modeling with SystemC: TLM Concepts and Applications for Embedded Systems","author":"F Ghenassia","year":"2006","unstructured":"Ghenassia, F.: Transaction-Level Modeling with SystemC: TLM Concepts and Applications for Embedded Systems. Springer, New York (2006). https:\/\/doi.org\/10.1007\/b137175"},{"key":"11_CR18","doi-asserted-by":"publisher","first-page":"237","DOI":"10.1007\/978-1-4615-1481-7_6","volume-title":"System Design","author":"Andreas Gerstlauer","year":"2001","unstructured":"Gerstlauer, A., D\u00f6mer, R., Peng, J., Gajski, D.D.: System Design: A Practical Guide with SpecC. Springer, Heidelberg (2001). https:\/\/doi.org\/10.1007\/978-1-4615-1481-7"},{"key":"11_CR19","unstructured":"Fulgham, M.L., Snyder, L.: Performance of chaos and oblivious routers under non-uniform traffic. Technical report (1993)"},{"key":"11_CR20","doi-asserted-by":"crossref","unstructured":"Mello, A., Tedesco, L., Calazans, N., Moraes, F.: Virtual channels in networks on chip: implementation and evaluation on hermes NoC. In: Integrated Circuits and System Design, pp. 178\u2013183. ACM (2005)","DOI":"10.1109\/SBCCI.2005.4286853"}],"container-title":["IFIP Advances in Information and Communication Technology","System Level Design from HW\/SW to Memory for Embedded Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-319-90023-0_11","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,3]],"date-time":"2025-07-03T18:02:54Z","timestamp":1751565774000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-319-90023-0_11"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017]]},"ISBN":["9783319900223","9783319900230"],"references-count":20,"URL":"https:\/\/doi.org\/10.1007\/978-3-319-90023-0_11","relation":{},"ISSN":["1868-4238","1868-422X"],"issn-type":[{"type":"print","value":"1868-4238"},{"type":"electronic","value":"1868-422X"}],"subject":[],"published":{"date-parts":[[2017]]},"assertion":[{"value":"17 April 2018","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"IESS","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"International Embedded Systems Symposium","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Foz do Igua\u00e7u","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Brazil","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2015","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"3 November 2015","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"6 November 2015","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"5","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"iess2015","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"http:\/\/www.iess.org\/","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"This content has been made available to all.","name":"free","label":"Free to read"}]}}