{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,10]],"date-time":"2024-09-10T21:06:39Z","timestamp":1726002399821},"publisher-location":"Cham","reference-count":39,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783319993218"},{"type":"electronic","value":"9783319993225"}],"license":[{"start":{"date-parts":[[2018,12,6]],"date-time":"2018-12-06T00:00:00Z","timestamp":1544054400000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019]]},"DOI":"10.1007\/978-3-319-99322-5_20","type":"book-chapter","created":{"date-parts":[[2018,12,5]],"date-time":"2018-12-05T12:56:24Z","timestamp":1544014584000},"page":"399-416","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Approximate Cache Architectures"],"prefix":"10.1007","author":[{"given":"Natalie Enright","family":"Jerger","sequence":"first","affiliation":[]},{"given":"Joshua San","family":"Miguel","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2018,12,6]]},"reference":[{"key":"20_CR1","doi-asserted-by":"crossref","unstructured":"Alameldeen A, Wood DA (2004) Adaptive cache compression for high-performance processors. In: International symposium on computer architecture","DOI":"10.1109\/ISCA.2004.1310776"},{"key":"20_CR2","doi-asserted-by":"crossref","unstructured":"Albericio J, Ibanez P, Vinals V, Llaberia JM (2013) The reuse cache: downsizing the shared last-level cache. In: Proceedings of the international symposium on microarchitecture","DOI":"10.1145\/2540708.2540735"},{"key":"20_CR3","doi-asserted-by":"publisher","first-page":"922","DOI":"10.1109\/TC.2005.119","volume":"54","author":"C Alvarez","year":"2005","unstructured":"Alvarez C, Corbal J, Valero M (2005) Fuzzy memoization for floating-point multimedia applications. IEEE Trans Comput 54:922\u2013927","journal-title":"IEEE Trans Comput"},{"key":"20_CR4","doi-asserted-by":"crossref","unstructured":"Biswas S, Franklin D, Savage A, Dixon R, Sherwood T, Chong F (2009) Multi-execution: multicore caching for data-similar executions. In: Proceedings of the international symposium on computer architecture","DOI":"10.1145\/1555754.1555777"},{"key":"20_CR5","unstructured":"Burtscher M (2000) Improving context-based load value prediction. PhD Thesis, University of Colorado"},{"key":"20_CR6","doi-asserted-by":"publisher","first-page":"182","DOI":"10.1145\/1138035.1138038","volume":"3","author":"L Ceze","year":"2006","unstructured":"Ceze L, Strauss K, Tuck J, Torrellas J, Renau J (2006) CAVA: using checkpoint-assisted value prediction to hide L2 misses. ACM Trans Archit Code Optim 3:182\u2013208","journal-title":"ACM Trans Archit Code Optim"},{"key":"20_CR7","first-page":"8","volume":"18","author":"X Chen","year":"2010","unstructured":"Chen X, Yang L, Dick RP, Shang L, Lekatsas H (2010) C-pack: a high-performance microprocessor cache compression algorithm. IEEE Trans Very Large Scale Integr 18:8","journal-title":"IEEE Trans Very Large Scale Integr"},{"issue":"1","key":"20_CR8","doi-asserted-by":"publisher","first-page":"1","DOI":"10.2200\/S00581ED1V01Y201405CAC028","volume":"9","author":"Babak Falsafi","year":"2014","unstructured":"Falsafi B, Wenisch T (2014) A Primer on hardware prefetching. Morgan Claypool, San Rafael","journal-title":"Synthesis Lectures on Computer Architecture"},{"key":"20_CR9","doi-asserted-by":"crossref","unstructured":"Fluhr E, Friedrich J, Dreps D, Zyuban V, Still G, Gonzalez C, Hall A, Hogenmiller D, Malgioglio F, Nett R, Paredes J, Pille J, Plass D, Puri R, Restle P, Shan D, Stawiasz K, Deniz ZT, Wendel D, Ziegler M (2014) POWER8TM: a 12-core server-class processor in 22nm SOI with 7.6tb\/s off-chip bandwidth. In: Proceedings of the international solid state circuits conference","DOI":"10.1109\/ISSCC.2014.6757353"},{"key":"20_CR10","unstructured":"Gabbay F (1996) Speculative execution based on value prediction. EE Department Technical Report 1080, Technion - Israel Institute of Technology"},{"key":"20_CR11","doi-asserted-by":"crossref","unstructured":"Hallnor E, Reinhardt S (2005) A unified compressed memory hierarchy. In: Proceedings of the international symposium on high performance computer architecture","DOI":"10.1109\/HPCA.2005.4"},{"key":"20_CR12","doi-asserted-by":"publisher","first-page":"2","DOI":"10.1109\/MM.2014.10","volume":"34","author":"P Hammarlund","year":"2014","unstructured":"Hammarlund P, Martinez A, Bajwa A, Hill D, Hallnor E, Jiang H, Dixon M, Derr M, Hunsaker M, Kumar R, Osborne R, Rajwar R, Singhal R, D\u2019Sa R, Chappell R, Kaushik S, Chennupaty S, Jourdan S, Gunther S, Piazza T, Burton T (2014) Haswell: the fourth-generation intel core processor. IEEE Micro 34:2","journal-title":"IEEE Micro"},{"key":"20_CR13","doi-asserted-by":"crossref","unstructured":"Jaleel A, Theobald KB, Steely SC Jr, Emer J (2010) High performance cache replacement using re-reference interval prediction (RRIP). In: proceedings of the 38th international symposium on computer architecture","DOI":"10.1145\/1816038.1815971"},{"key":"20_CR14","unstructured":"Khan SM, Tian Y, Jim\u00e9nez DA (2010) Dead block replacement and bypass with a sampling predictor. In: Proceedings of the 43rd international symposium on microarchitecture"},{"key":"20_CR15","doi-asserted-by":"crossref","unstructured":"Kharbutli M, Irwin K, Solihin Y, Lee J (2004) Using prime numbers for cache indexing to eliminate conflict misses. In: HPCA","DOI":"10.1109\/HPCA.2004.10015"},{"key":"20_CR16","doi-asserted-by":"crossref","unstructured":"Kleanthous M, Sazeides Y (2008) CATCH: a mechanism for dynamically detecting cache-content-duplication and its application to instruction caches. In: Proceedings of the conference on design automation and test in Europe","DOI":"10.1145\/1403375.1403720"},{"key":"20_CR17","doi-asserted-by":"crossref","unstructured":"Lipasti MH, Wilkerson CB, Shen JP (1996) Value locality and load value prediction. In: Proceedings of the international conference architectural support for programming languages and operating systems","DOI":"10.1145\/237090.237173"},{"key":"20_CR18","doi-asserted-by":"publisher","first-page":"759","DOI":"10.1109\/TC.2009.28","volume":"58","author":"S Liu","year":"2009","unstructured":"Liu S, Gaudiot J (2009) Potential impact of value prediction on communication in many-core architectures. IEEE Trans Comput 58:759\u2013769","journal-title":"IEEE Trans Comput"},{"key":"20_CR19","doi-asserted-by":"crossref","unstructured":"Martin MMK, Sorin DJ, Cain HW, Hill MD, Lipasti MH (2001) Correctly implementing value prediction in microprocessors that support multithreading or multiprocessing. In: Proceedings of the international symposium on microarchitecture","DOI":"10.1109\/MICRO.2001.991130"},{"key":"20_CR20","doi-asserted-by":"crossref","unstructured":"Nakra T, Gupta R, Soffa ML (1999) Global context-based value prediction. In: Proceedings of the international symposium high-performance computer architecture","DOI":"10.1109\/HPCA.1999.744311"},{"key":"20_CR21","doi-asserted-by":"crossref","unstructured":"Pekhimenko G, Seshadr V, Mutlu O, Kozuch M, Gibbons PB, Mowry TC (2012) Base-delta-immediate compression: Practical data compression for on-chip caches. In: Proceedings of the international conference on parallel architecture and compilation techniques","DOI":"10.1145\/2370816.2370870"},{"key":"20_CR22","doi-asserted-by":"crossref","unstructured":"Qureshi MK, Jaleel A, Patt YN, Steely SC Jr, Emer J (2007) Adaptive insertion policies for high performance caching. In: Proceedings of the 34th international symposium on computer architecture","DOI":"10.1145\/1250662.1250709"},{"key":"20_CR23","doi-asserted-by":"crossref","unstructured":"San Miguel J, Badr M, Enright Jerger N (2014) Load value approximation. In: International symposium on microarchitecture","DOI":"10.1109\/MICRO.2014.22"},{"key":"20_CR24","doi-asserted-by":"crossref","unstructured":"San Miguel J, Albericio J, Moshovos A, Enright Jerger N (2015) Doppelganger: a cache for approximate computing. In: MICRO","DOI":"10.1145\/2830772.2830790"},{"key":"20_CR25","doi-asserted-by":"crossref","unstructured":"San Miguel J, Albericio J, Enright Jerger N, Jaleel A (2016) The bunker cache for spatio-value approximation. In: MICRO","DOI":"10.1109\/MICRO.2016.7783746"},{"key":"20_CR26","doi-asserted-by":"crossref","unstructured":"Sardashti S, Wood DA (2013) Decoupled compressed cache: exploiting spatial locality for energy-optimized compressed caching. In: International symposium on microarchitecture","DOI":"10.1145\/2540708.2540715"},{"key":"20_CR27","doi-asserted-by":"crossref","unstructured":"Sardashti S, Seznec A, Wood DA (2014) Skewed compressed cache. In: International symposium on microarchitecture","DOI":"10.1109\/MICRO.2014.41"},{"key":"20_CR28","doi-asserted-by":"crossref","unstructured":"Sazeides Y, Smith J (1997) The predictability of data values. In: Proceedings of the international symposium microarchitecture","DOI":"10.1109\/MICRO.1997.645815"},{"key":"20_CR29","doi-asserted-by":"publisher","first-page":"3","DOI":"10.1109\/L-CA.2003.3","volume":"2","author":"R Sendag","year":"2003","unstructured":"Sendag R, Chuang P-F, Lilja D (2003) Address correlation: exceeding the limits of locality. IEEE Comput Archit Lett 2:3\u20133","journal-title":"IEEE Comput Archit Lett"},{"key":"20_CR30","doi-asserted-by":"crossref","unstructured":"Seznec A (1993) A case for two-way skewed-associative caches. In: Proceedings of the international symposium computer architecture","DOI":"10.1145\/165123.165152"},{"key":"20_CR31","doi-asserted-by":"crossref","unstructured":"Sreeram J, Pande S (2010) Exploiting approximate value locality for data synchronization on multi-core processors. In: Proceedings of the international symposium workload characterization","DOI":"10.1109\/IISWC.2010.5650333"},{"key":"20_CR32","doi-asserted-by":"crossref","unstructured":"Thwaites B, Pekhimenko G, Esmaeilzadeh H, Yazdanbakhsh A, Mutlu O, Park J, Mururu G, Mowry T (2014) Rollback-free value prediction with approximate loads. Poster presented at PACT","DOI":"10.1145\/2628071.2628110"},{"key":"20_CR33","doi-asserted-by":"crossref","unstructured":"Tian Y, Khan S, Jimenez D, Loh G (2014) Last-level cache deduplication. In: Proceedings of the international conference on supercomputing","DOI":"10.1145\/2597652.2597655"},{"key":"20_CR34","doi-asserted-by":"publisher","first-page":"273","DOI":"10.1109\/92.845894","volume":"8","author":"JYF Tong","year":"2000","unstructured":"Tong JYF, Nagle D, Rutenbar RA (2000) Reducing power by optimizing the necessary precision\/range of floating-point arithmetic. IEEE Trans Very Large Scale Integr Syst 8:273\u2013286","journal-title":"IEEE Trans Very Large Scale Integr Syst"},{"key":"20_CR35","doi-asserted-by":"crossref","unstructured":"Wong D, Kim NS, Annavaram M (2016) Approximating warps with intra-warp operand value similarity. In: Proceedings of the international symposium on high performance computer architecture","DOI":"10.1109\/HPCA.2016.7446063"},{"key":"20_CR36","doi-asserted-by":"crossref","unstructured":"Wu CJ, Jaleel A, Martonosi M, Steely S Jr, Emer J (2011) PACMan: prefetch-aware cache management for high performance caching. In: Proceedings of the international symposium on microarchitecture","DOI":"10.1145\/2155620.2155672"},{"key":"20_CR37","doi-asserted-by":"publisher","first-page":"4","DOI":"10.1145\/2836168","volume":"12","author":"A Yazdanbakhsh","year":"2016","unstructured":"Yazdanbakhsh A, Pekhimenko G, Thwaites B, Esmaeilzadeh H, Mutlu O, Mowry TC (2016) RFVP: rollback-free value prediction with safe-to-approximate loads. ACM Trans Archit Code Optim 12:4","journal-title":"ACM Trans Archit Code Optim"},{"key":"20_CR38","doi-asserted-by":"publisher","first-page":"150","DOI":"10.1145\/384264.379235","volume":"34","author":"Y Zhang","year":"2000","unstructured":"Zhang Y, Yang J, Gupta R (2000) Frequent value locality and value-centric data cache design. ACM SIGOPS Oper Syst Rev 34:150\u2013159","journal-title":"ACM SIGOPS Oper Syst Rev"},{"key":"20_CR39","doi-asserted-by":"crossref","unstructured":"Zhou H, Flanagan J, Conte TM (2003) Detecting global stride locality in value streams. In: Proceedings of the international symposium computer architecture","DOI":"10.1145\/859618.859656"}],"container-title":["Approximate Circuits"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-319-99322-5_20","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,11,6]],"date-time":"2019-11-06T15:38:59Z","timestamp":1573054739000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-319-99322-5_20"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,12,6]]},"ISBN":["9783319993218","9783319993225"],"references-count":39,"URL":"https:\/\/doi.org\/10.1007\/978-3-319-99322-5_20","relation":{},"subject":[],"published":{"date-parts":[[2018,12,6]]}}}