{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,1]],"date-time":"2025-03-01T16:10:03Z","timestamp":1740845403695,"version":"3.38.0"},"publisher-location":"Berlin, Heidelberg","reference-count":11,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540223771"},{"type":"electronic","value":"9783540277767"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2004]]},"DOI":"10.1007\/978-3-540-27776-7_21","type":"book-chapter","created":{"date-parts":[[2011,1,10]],"date-time":"2011-01-10T17:33:28Z","timestamp":1294680808000},"page":"192-202","source":"Crossref","is-referenced-by-count":6,"title":["The Virtex II ProTM MOLEN Processor"],"prefix":"10.1007","author":[{"given":"Georgi","family":"Kuzmanov","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Georgi","family":"Gaydadjiev","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Stamatis","family":"Vassiliadis","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"21_CR1","doi-asserted-by":"crossref","unstructured":"Campi, F., Toma, M., Lodi, A., Cappelli, A., Canegallo, R., Guerrieri, R.: VLIW Processor with Reconfigurable Instruction Set for Embedded Applications. In: ISSCC Digest of Technical Papers, February 2003, pp. 250\u2013251 (2003)","DOI":"10.1109\/ISSCC.2003.1234288"},{"key":"21_CR2","doi-asserted-by":"crossref","unstructured":"Gokhale, M., Stone, J.: Napa C: Compiling for a Hybrid RISC\/FPGA Architecture. In: Proc. IEEE Symp. on FCCM, pp. 126\u2013135 (1998)","DOI":"10.1109\/FPGA.1998.707890"},{"key":"21_CR3","doi-asserted-by":"crossref","unstructured":"Hauck, S., Fry, T., Hosler, M., Kao, J.: The Chimaera Reconfigurable Functional Unit. In: Proc. IEEE Symp. on FCCM, pp. 87\u201396 (1997)","DOI":"10.1109\/FPGA.1997.624608"},{"key":"21_CR4","doi-asserted-by":"crossref","unstructured":"Kuzmanov, G., Gaydadjiev, G.N., Vassiliadis, S.: Loading rm-code: Design considerations. In: Proc. Third Intl. Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS 2003), pp. 8\u201311 (2003)","DOI":"10.1007\/978-3-540-27776-7_2"},{"key":"21_CR5","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"81","DOI":"10.1007\/978-3-540-45234-8_9","volume-title":"Field Programmable Logic and Application","author":"G. Kuzmanov","year":"2003","unstructured":"Kuzmanov, G., Vassiliadis, S.: Arbitrating Instructions in an \u03c1\u03bc-coded CCM. In: Y. K. Cheung, P., Constantinides, G.A. (eds.) FPL 2003. LNCS, vol.\u00a02778, pp. 81\u201390. Springer, Heidelberg (2003)"},{"key":"21_CR6","doi-asserted-by":"crossref","unstructured":"Rosa, L., Lavagno, L., Passerone, C.: Hardware\/Software Design Space Exploration for a Reconfigurable Processor. In: Proc. DATE 2003, pp. 570\u2013575 (2003)","DOI":"10.1109\/DATE.2003.1253669"},{"key":"21_CR7","doi-asserted-by":"crossref","unstructured":"Vassiliadis, S., Gaydadjiev, G.N., Bertels, K., Panainte, E.M.: The molen programming paradigm. In: Proc. Third Intl.Workshop on Systems, Architectures,Modeling, and Simulation (SAMOS 2003) , pp. 1\u20137 (2003)","DOI":"10.1007\/978-3-540-27776-7_1"},{"key":"21_CR8","doi-asserted-by":"crossref","unstructured":"Vassiliadis, S., Hakkennes, E., Wong, S., Pechanek, G.: The Sum-of-Absolute-Difference Motion Estimation Accelerator. In: Proc. 24th Euromicro Conf., pp. 559\u2013566 (1998)","DOI":"10.1109\/EURMIC.1998.708071"},{"key":"21_CR9","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"275","DOI":"10.1007\/3-540-44687-7_29","volume-title":"Field-Programmable Logic and Applications","author":"S. Vassiliadis","year":"2001","unstructured":"Vassiliadis, S., Wong, S., Cotofana, S.: The MOLEN \u03c1\u03bc-coded processor. In: Brebner, G., Woods, R. (eds.) FPL 2001. LNCS, vol.\u00a02147, pp. 275\u2013285. Springer, Heidelberg (2001)"},{"key":"21_CR10","unstructured":"Xilinx Corporation. Virtex-II Pro Platform FPGA Handbook, v.1.0 (2002)"},{"key":"21_CR11","doi-asserted-by":"crossref","unstructured":"Ye, A., Shenoy, N., Banerjee, P.: A C Compiler for a Processor with a Reconfigurable Functional Unit. In: ACM\/SIGDA Symp. on FPGAs, pp. 95\u2013100 (2000)","DOI":"10.1145\/329166.329187"}],"container-title":["Lecture Notes in Computer Science","Computer Systems: Architectures, Modeling, and Simulation"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-27776-7_21.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,1]],"date-time":"2025-03-01T15:45:29Z","timestamp":1740843929000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-27776-7_21"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2004]]},"ISBN":["9783540223771","9783540277767"],"references-count":11,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-27776-7_21","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2004]]}}}