{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,27]],"date-time":"2026-03-27T03:36:38Z","timestamp":1774582598841,"version":"3.50.1"},"publisher-location":"Berlin, Heidelberg","reference-count":14,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"value":"9783540223771","type":"print"},{"value":"9783540277767","type":"electronic"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2004]]},"DOI":"10.1007\/978-3-540-27776-7_53","type":"book-chapter","created":{"date-parts":[[2011,1,10]],"date-time":"2011-01-10T17:33:28Z","timestamp":1294680808000},"page":"519-529","source":"Crossref","is-referenced-by-count":8,"title":["High-Speed Event-Driven RTL Compiled Simulation"],"prefix":"10.1007","author":[{"given":"Alexey","family":"Kupriyanov","sequence":"first","affiliation":[]},{"given":"Frank","family":"Hannig","sequence":"additional","affiliation":[]},{"given":"J\u00fcrgen","family":"Teich","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"53_CR1","unstructured":"Mips homepage, http:\/\/mips.com\/"},{"key":"53_CR2","unstructured":"Synopsys homepage, http:\/\/synopsys.com\/"},{"key":"53_CR3","unstructured":"Axys design automation, http:\/\/www.axysdesign.com"},{"key":"53_CR4","unstructured":"Daniel, J.Z.: A retargetable, ultra-fast instruction set simulator. In: Proceedings on the European Design and Test Conference (1999)"},{"key":"53_CR5","unstructured":"Sentovich, K.S.E., et al.: Sis: A system for sequential circuit synthesis. In: Technical Report UCB\/ERL M92\/41. University of California, Berkeley (May 1992)"},{"key":"53_CR6","doi-asserted-by":"crossref","unstructured":"Fischer, D., Teich, J., Thies, M., Weper, R.: Efficient architecture\/compiler co-exploration for asips. In: ACM SIG Proceedings International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES 2002), Grenoble, France, pp. 27\u201334 (2002)","DOI":"10.1145\/581630.581635"},{"key":"53_CR7","doi-asserted-by":"crossref","unstructured":"Fischer, D., Teich, J., Thies, M., Weper, R.: BUILDABONG: A framework for architecture\/ compiler co-exploration for ASIPs. Journal for Circuits, Systems, and Computers, Special Issue: Application Specific Hardware Design, 353\u2013375 (2003)","DOI":"10.1142\/S0218126603000799"},{"key":"53_CR8","unstructured":"Granlund, T.: The GNU multiple precision library, edn. 2.0.2. Technical report, TMG Datakonsult, Sodermannagatan 5, 11623 Stockholm, Sweden (1996)"},{"key":"53_CR9","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4757-2570-4","volume-title":"Retargetable Code Generation for Digital Signal Processors","author":"R. Leupers","year":"1997","unstructured":"Leupers, R.: Retargetable Code Generation for Digital Signal Processors. Kluwer Academic Publishers, Dordrecht (1997)"},{"key":"53_CR10","doi-asserted-by":"crossref","unstructured":"Pees, S., Hoffmann, A., Meyr, H.: Retargeting of compiled simulators for digital signal processors using a machine description language. In: Proceedings Design Automation and Test in Europe (DATE 2000), Paris (March 2000)","DOI":"10.1145\/343647.343888"},{"key":"53_CR11","doi-asserted-by":"crossref","unstructured":"Schnarr, E., Larus, J.R.: Fast out-of-order processor simulation using memorization. In: Proceedings of the eighth international conference on Architectural support for programming languages and operating systems, pp. 283\u2013294 (1998)","DOI":"10.1145\/291069.291063"},{"key":"53_CR12","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"266","DOI":"10.1007\/3-540-44518-8_15","volume-title":"Abstract State Machines - Theory and Applications","author":"J. Teich","year":"2000","unstructured":"Teich, J., Kutter, P., Weper, R.: Description and simulation of microprocessor instruction sets using asms. In: Gurevich, Y., Kutter, P.W., Odersky, M., Thiele, L. (eds.) ASM 2000. LNCS, vol.\u00a01912, pp. 266\u2013286. Springer, Heidelberg (2000)"},{"key":"53_CR13","doi-asserted-by":"crossref","unstructured":"Wang, L.-T., Hoover, N.E., Porter, E.H., Zasio, J.J.: SSIM: A software levelized compiledcode simulator, 2\u20138","DOI":"10.1145\/37888.37889"},{"key":"53_CR14","doi-asserted-by":"crossref","unstructured":"Witchel, E., Rosenblum, M.: Embra: Fast and flexible machine simulation. In: Measurement and Modeling of Computer Systems , 68\u201379 (1996)","DOI":"10.1145\/233008.233025"}],"container-title":["Lecture Notes in Computer Science","Computer Systems: Architectures, Modeling, and Simulation"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-27776-7_53.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,1]],"date-time":"2025-03-01T15:45:39Z","timestamp":1740843939000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-27776-7_53"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2004]]},"ISBN":["9783540223771","9783540277767"],"references-count":14,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-27776-7_53","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"value":"0302-9743","type":"print"},{"value":"1611-3349","type":"electronic"}],"subject":[],"published":{"date-parts":[[2004]]}}}