{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T19:55:37Z","timestamp":1725566137058},"publisher-location":"Berlin, Heidelberg","reference-count":12,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540230038"},{"type":"electronic","value":"9783540301028"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2004]]},"DOI":"10.1007\/978-3-540-30102-8_41","type":"book-chapter","created":{"date-parts":[[2010,9,16]],"date-time":"2010-09-16T14:38:53Z","timestamp":1284647933000},"page":"489-502","source":"Crossref","is-referenced-by-count":0,"title":["Dynamic Fetch Engine for Simultaneous Multithreaded Processors"],"prefix":"10.1007","author":[{"given":"Tzung-Rei","family":"Yang","sequence":"first","affiliation":[]},{"given":"Jong-Jiann","family":"Shieh","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"41_CR1","doi-asserted-by":"crossref","unstructured":"Dorai, G., Yeung, D.: Transparent threads: resource sharing in SMT processors for high single-thread performance. In: 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), September 22-25 (2002)","DOI":"10.1109\/PACT.2002.1105971"},{"key":"41_CR2","unstructured":"Eggers, S., Emer, J., Levy, H., Lo, J., Stamm, R., Tullsen, D.: Simultaneous multi-threading: A platform for next-generation processors. Technical Report TR-97-04-02, Uni\u00acversity of Washington, Department of Computer Science and Engineering (April 1997)"},{"key":"41_CR3","doi-asserted-by":"crossref","unstructured":"El-Moursy, A., Albonesi, D.: Front-end policies for improved issue efficiency in SMT processors. In: 9th International Symposium on High-Performance Computer Architecture, February 2003, pp. 31\u201340 (2003)","DOI":"10.1109\/HPCA.2003.1183522"},{"key":"41_CR4","doi-asserted-by":"crossref","unstructured":"Hirata, H., Kimura, K., Nagamine, S., Mochizuki, Y., Nishimura, A., Nakase, Y., Nishi-zawa, T.: An elementary processor architecture with simultaneous instruction issuing from multiple threads. In: 19th Annual International Symposium on Computer Architecture, May 1992, pp. 136\u2013145 (1992)","DOI":"10.1145\/139669.139710"},{"key":"41_CR5","doi-asserted-by":"crossref","unstructured":"Knijnenburg, P.M.W., Ramirez, A., Latorre, F., Larriba, J., Valero, M.: Branch classification to control instruction fetch in simultaneous multithreaded architectures. In: International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA 2002), January 10-11 (2002)","DOI":"10.1109\/IWIA.2002.1035020"},{"key":"41_CR6","doi-asserted-by":"crossref","unstructured":"Lo, J., Eggers, S., Emer, J., Levy, H., Stamm, R., Tullsen, D.: Converting thread-level parallelism into instruction-Level parallelism via simultaneous multithreading. In: ACM Transactions on Computer Systems, August 1997, pp. 322\u2013354 (1997)","DOI":"10.1145\/263326.263382"},{"key":"41_CR7","unstructured":"Luo, K., Franklin, M., Mukherjee, S., Sezne, A.: Boosting SMT performance by specula\u00action control. In: 15th Proceedings of International Parallel and Distributed Processing Symposium, IPDPS (2001)"},{"key":"41_CR8","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"716","DOI":"10.1007\/3-540-48311-X_101","volume-title":"Euro-Par\u201999 Parallel Processing","author":"D. Madon","year":"1999","unstructured":"Madon, D., Sanchez, E., Monnier, S.: A Study of a Simultaneous Multithreaded Architecture. In: Amestoy, P.R., Berger, P., Dayd\u00e9, M., Duff, I.S., Frayss\u00e9, V., Giraud, L., Ruiz, D. (eds.) Euro-Par 1999. LNCS, vol.\u00a01685, pp. 716\u2013726. Springer, Heidelberg (1999)"},{"key":"41_CR9","unstructured":"Marr, D., Binns, F., Hill, D., Hinton, G., Koufaty, D., Miller, J., Upton, M.: Hyper-threading technology architecture and microarchitecture. Intel Technology Journal, 4\u201315 (February 2002)"},{"key":"41_CR10","doi-asserted-by":"crossref","unstructured":"Tullsen, D., Eggers, S., Emer, J., Levy, H., Lo, J., Stamm, R.: Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor. In: 23rd Annul International Symposium on Computer Architecture (May 1996)","DOI":"10.1145\/232973.232993"},{"key":"41_CR11","doi-asserted-by":"crossref","unstructured":"Tullsen, D., Brown, J.: Handling long-latency loads in a simultaneous multithreading processor. In: 34th Annual International Symposium on Microarchitecture (December 2001)","DOI":"10.1109\/MICRO.2001.991129"},{"key":"41_CR12","doi-asserted-by":"crossref","unstructured":"Tullsen, D., Eggers, S., Levy, H.: Simultaneous multithreading: Maximizing on-chip parallelism. In: 22nd Annul International Symposium on Computer Architecture (June 1995)","DOI":"10.1145\/223982.224449"}],"container-title":["Lecture Notes in Computer Science","Advances in Computer Systems Architecture"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-30102-8_41.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,11,18]],"date-time":"2020-11-18T23:40:12Z","timestamp":1605742812000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-30102-8_41"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2004]]},"ISBN":["9783540230038","9783540301028"],"references-count":12,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-30102-8_41","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2004]]}}}