{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,11]],"date-time":"2025-04-11T05:28:45Z","timestamp":1744349325395},"publisher-location":"Berlin, Heidelberg","reference-count":19,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540229896"},{"type":"electronic","value":"9783540301172"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2004]]},"DOI":"10.1007\/978-3-540-30117-2_17","type":"book-chapter","created":{"date-parts":[[2010,9,18]],"date-time":"2010-09-18T09:01:02Z","timestamp":1284800462000},"page":"145-157","source":"Crossref","is-referenced-by-count":31,"title":["A Dual-V DD Low Power FPGA Architecture"],"prefix":"10.1007","author":[{"given":"A.","family":"Gayasen","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"K.","family":"Lee","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"N.","family":"Vijaykrishnan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Kandemir","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M. J.","family":"Irwin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"T.","family":"Tuan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"17_CR1","doi-asserted-by":"crossref","unstructured":"Anderson, J.H., Najm, F., Tuan, T.: Active Leakage Power Optimization for FPGAs. In: Proceedings of ACM\/SIGDA International Symposium on Fieldprogrammable gate arrays (2004)","DOI":"10.1145\/968280.968287"},{"key":"17_CR2","doi-asserted-by":"crossref","unstructured":"Betz, V., Rose, J.: VPR: A New Packing, Placement and Routing Tool for FPGA Research. In: International Workshop on Field-programmable Logic and Applications (1997)","DOI":"10.1007\/3-540-63465-7_226"},{"key":"17_CR3","doi-asserted-by":"crossref","unstructured":"Calhoun, B., Honore, F., Chandrakasan, A.: Design Methodology for Finegrained Leakage Control in MTCMOS. In: Proceedings of International Symposium on Low Power Electronics and Design (2003)","DOI":"10.1145\/871534.871535"},{"key":"17_CR4","volume-title":"Design of High-Performance Microprocessor Circuits","author":"A. Chandrakasan","year":"2001","unstructured":"Chandrakasan, A., Bowhill, W., Fox, F.: Design of High-Performance Microprocessor Circuits. IEEE Press, Los Alamitos (2001)"},{"key":"17_CR5","doi-asserted-by":"crossref","unstructured":"Chen, D., Cong, J., Li, F., He, L.: Low-Power Technology Mapping for FPGA Architectures with Dual Supply Voltages. In: Proceedings of International Symposium on Field-programmable gate arrays (2004)","DOI":"10.1145\/968280.968297"},{"key":"17_CR6","doi-asserted-by":"crossref","unstructured":"Gayasen, A., Tsai, Y., Vijaykrishnan, N., Kandemir, M., Irwin, M.J., Tuan, T.: Reducing leakage energy in FPGAs using region-constrained placement. In: Proceedings of International Symposium on Field-programmable gate arrays (2004)","DOI":"10.1145\/968280.968289"},{"key":"17_CR7","doi-asserted-by":"crossref","unstructured":"George, V., Zhang, H., Rabaey, J.: The design of a low energy FPGA. In: Proceedings of International Symposium on Low Power Electronics and Design (1999)","DOI":"10.1145\/313817.313920"},{"key":"17_CR8","doi-asserted-by":"crossref","unstructured":"Ju, Y.-C., Saleh, R.A.: Incremental Techniques for the Identification of Statically Sensitizable Critical Paths. In: Design Automation Conference (1991)","DOI":"10.1145\/127601.127729"},{"key":"17_CR9","doi-asserted-by":"crossref","unstructured":"Kusse, E., Rabaey, J.: Low-Energy Embedded FPGA Structures. In: Proceedings of International Symposium on Low Power Electronics and Design (1998)","DOI":"10.1145\/280756.280873"},{"key":"17_CR10","doi-asserted-by":"crossref","unstructured":"Li, F., Chen, D., He, L., Cong, J.: Architecture Evaluation for Power-Efficient FPGAs. In: Proceedings of ACM\/SIGDA International Symposium on Fieldprogrammable gate arrays (2003)","DOI":"10.1145\/611817.611844"},{"key":"17_CR11","doi-asserted-by":"crossref","unstructured":"Li, F., Lin, Y., He, L., Cong, J.: Low-power FPGA using Pre-Defined Dual- Vdd\/Dual-Vt Fabrics. In: Proceedings of ACM\/SIGDA International Symposium on Field-programmable gate arrays (2004)","DOI":"10.1145\/968280.968288"},{"key":"17_CR12","doi-asserted-by":"crossref","unstructured":"Poon, K., Yan, A., Wilton, S.: A flexible Power Model for FPGAs. In: Proceedings of International Conference on Field Programmable Logic and Applications (2002)","DOI":"10.1007\/3-540-46117-5_33"},{"key":"17_CR13","doi-asserted-by":"crossref","unstructured":"Puri, R., Stok, L., Cohn, J., Kung, D., Pan, D., Sylvester, D., Srivastava, A., Kulkarni, S.: Pushing ASIC performance in a power envelope. In: Design Automation Conference (2003)","DOI":"10.1145\/775832.776032"},{"key":"17_CR14","doi-asserted-by":"crossref","unstructured":"Rahman, A., Polavarapuv, V.: Evaluation of Low-Leakage Design Techniques for Field Programmable Gate Arrays. In: Proceedings of ACM\/SIGDA International Symposium on Field-programmable gate arrays (2004)","DOI":"10.1145\/968280.968285"},{"key":"17_CR15","doi-asserted-by":"crossref","unstructured":"Shang, L., Kaviani, A.S., Bathala, K.: Dynamic power consumption in Virtex[tm]-II FPGA family. In: Proceedings of ACM\/SIGDA International Symposium on Field-programmable gate arrays (2002)","DOI":"10.1145\/503048.503072"},{"key":"17_CR16","doi-asserted-by":"crossref","unstructured":"Singh, A., Marek-Sadowska, M.: Efficient Circuit Clustering for Area and Power Reduction in FPGAs. In: Proceedings of ACM\/SIGDA International Symposium on Field-programmable gate arrays (2002)","DOI":"10.1145\/503048.503058"},{"key":"17_CR17","doi-asserted-by":"crossref","unstructured":"Takahashi, M., et al.: A 60-mW MPEG4 Video Codec Using Clustered Voltage Scaling with Variable Supply-Voltage Scheme. IEEE Journal of Solid-State Circuits\u00a033(11) (November 1998)","DOI":"10.1109\/4.726575"},{"key":"17_CR18","unstructured":"Tuan, T., Lai, B.: Leakage Power Analysis of a 90nm FPGA. In: Custom Integrated Circuits Conference (2003)"},{"key":"17_CR19","doi-asserted-by":"crossref","unstructured":"Usami, K., Horowitz, M.: Clustered voltage scaling technique for low-power design. In: Proceedings of International Symposium on Low Power Electronics and Design (1995)","DOI":"10.1145\/224081.224083"}],"container-title":["Lecture Notes in Computer Science","Field Programmable Logic and Application"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-30117-2_17.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,11,19]],"date-time":"2020-11-19T04:41:12Z","timestamp":1605760872000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-30117-2_17"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2004]]},"ISBN":["9783540229896","9783540301172"],"references-count":19,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-30117-2_17","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2004]]}}}