{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,26]],"date-time":"2025-03-26T17:47:55Z","timestamp":1743011275929,"version":"3.38.0"},"publisher-location":"Berlin, Heidelberg","reference-count":11,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540229896"},{"type":"electronic","value":"9783540301172"}],"license":[{"start":{"date-parts":[[2004,1,1]],"date-time":"2004-01-01T00:00:00Z","timestamp":1072915200000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2004]]},"DOI":"10.1007\/978-3-540-30117-2_19","type":"book-chapter","created":{"date-parts":[[2010,9,18]],"date-time":"2010-09-18T09:01:02Z","timestamp":1284800462000},"page":"168-178","source":"Crossref","is-referenced-by-count":3,"title":["Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis"],"prefix":"10.1007","author":[{"given":"Jason","family":"Anderson","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sudip","family":"Nag","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kamal","family":"Chaudhary","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sandor","family":"Kalman","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chari","family":"Madabhushi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Paul","family":"Cheng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"19_CR1","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"213","DOI":"10.1007\/3-540-63465-7_226","volume-title":"Field Programmable Logic and Applications","author":"V. Betz","year":"1997","unstructured":"Betz, V., Rose, J.: VPR: A new packing, placement and routing tool for FPGA research. In: Glesner, M., Luk, W. (eds.) FPL 1997. LNCS, vol.\u00a01304, pp. 213\u2013222. Springer, Heidelberg (1997)"},{"key":"19_CR2","doi-asserted-by":"publisher","first-page":"100","DOI":"10.1147\/rd.261.0100","volume":"26","author":"R.B. Hitchcock","year":"1982","unstructured":"Hitchcock, R.B., Smith, G.L., Cheng, D.D.: Timing analysis of computer hardware. IBM Jour. of Research and Development\u00a026, 100\u2013105 (1982)","journal-title":"IBM Jour. of Research and Development"},{"key":"19_CR3","doi-asserted-by":"crossref","first-page":"860","DOI":"10.1109\/43.31546","volume":"8","author":"R. Nair","year":"1989","unstructured":"Nair, R., Berman, C.L., Hauge, P.S., Yoffa, E.J.: Generation of performance constraints for layout. IEEE Transactions on CAD\u00a08, 860\u2013874 (1989)","journal-title":"IEEE Transactions on CAD"},{"key":"19_CR4","doi-asserted-by":"crossref","unstructured":"Youssef, H., Shragowitz, E.: Timing constraints for correct performance. In: Proc. of IEEE\/ACM ICCAD, pp. 24\u201327 (1990)","DOI":"10.1109\/ICCAD.1990.129830"},{"key":"19_CR5","doi-asserted-by":"crossref","unstructured":"Frankle, J.: Iterative and adaptive slack allocation for performance-driven layout and FPGA routing. In: Proc. of ACM\/IEEE DAC, pp. 536\u2013542 (1992)","DOI":"10.1109\/DAC.1992.227746"},{"key":"19_CR6","doi-asserted-by":"crossref","unstructured":"Marquardt, A., Betz, V., Rose, J.: Timing-driven placement for FPGAs. In: Proc. of ACM\/SIGDA FPGA, pp. 203\u2013213 (2000)","DOI":"10.1145\/329166.329208"},{"key":"19_CR7","doi-asserted-by":"crossref","unstructured":"McMurchie, L., Ebeling, C.: Pathfinder: A negotiation-based performance-driven router for FPGAs. In: Proc. of ACM\/SIGDA FPGA, pp. 111\u2013117 (1995)","DOI":"10.1109\/FPGA.1995.242049"},{"key":"19_CR8","doi-asserted-by":"crossref","unstructured":"Nag, S., Rutenbar, R.: Performance-driven simultaneous place and router for rowbased FPGAs. In: Proc. of IEEE\/ACM ICCAD, pp. 332\u2013338 (1995)","DOI":"10.1109\/ICCAD.1995.480137"},{"key":"19_CR9","doi-asserted-by":"publisher","first-page":"55","DOI":"10.1063\/1.1697872","volume":"19","author":"W. Elmore","year":"1948","unstructured":"Elmore, W.: The transient response of damped linear networks with particular regard to wideband amplifiers. Jour. of Applied Physics\u00a019, 55\u201362 (1948)","journal-title":"Jour. of Applied Physics"},{"key":"19_CR10","doi-asserted-by":"crossref","first-page":"202","DOI":"10.1109\/TCAD.1983.1270037","volume":"2","author":"J. Rubinstein","year":"1983","unstructured":"Rubinstein, J., Penfield, P., Horowitz, M.: Signal delay in RC tree networks. IEEE Transactions on CAD\u00a02, 202\u2013211 (1983)","journal-title":"IEEE Transactions on CAD"},{"key":"19_CR11","unstructured":"Xilinx: Virtex-II FPGA Data Book (2004)"}],"container-title":["Lecture Notes in Computer Science","Field Programmable Logic and Application"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-30117-2_19","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,25]],"date-time":"2025-02-25T22:31:09Z","timestamp":1740522669000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-30117-2_19"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2004]]},"ISBN":["9783540229896","9783540301172"],"references-count":11,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-30117-2_19","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2004]]}}}