{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T14:10:54Z","timestamp":1742393454869,"version":"3.38.0"},"publisher-location":"Berlin, Heidelberg","reference-count":16,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540229896"},{"type":"electronic","value":"9783540301172"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2004]]},"DOI":"10.1007\/978-3-540-30117-2_24","type":"book-chapter","created":{"date-parts":[[2010,9,18]],"date-time":"2010-09-18T09:01:02Z","timestamp":1284800462000},"page":"221-230","source":"Crossref","is-referenced-by-count":11,"title":["Second Order Function Approximation Using a Single Multiplication on FPGAs"],"prefix":"10.1007","author":[{"given":"J\u00e9r\u00e9mie","family":"Detrey","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Florent","family":"de Dinechin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"24_CR1","doi-asserted-by":"crossref","unstructured":"Cao, J., Wei, B.W.Y., Cheng, J.: High-performance architectures for elementary function generation. In: Burgess, N., Ciminiera, L. (eds.) 15th IEEE Symposium on Computer Arithmetic, Vail, Colorado (June 2001)","DOI":"10.1109\/ARITH.2001.930113"},{"key":"24_CR2","doi-asserted-by":"crossref","first-page":"17","DOI":"10.1109\/ARITH.1995.465381","volume-title":"12th IEEE Symposium on Computer Arithmetic","author":"D. Das Sarma","year":"1995","unstructured":"Das Sarma, D., Matula, D.W.: Faithful bipartite ROM reciprocal tables. In: Knowles, S., McAllister, W.H. (eds.) 12th IEEE Symposium on Computer Arithmetic, Bath, UK, pp. 17\u201328. IEEE Computer Society Press, Los Alamitos (1995)"},{"key":"#cr-split#-24_CR3.1","doi-asserted-by":"crossref","unstructured":"de Dinechin, F., Tisserand, A.: Some improvements on multipartite table methods. In: Burgess, N., Ciminiera, L. (eds.) 15th IEEE Symposium on Computer Arithmetic, Vail, Colorado, June 2001, pp. 128\u2013135 (2001);","DOI":"10.1109\/ARITH.2001.930112"},{"key":"#cr-split#-24_CR3.2","unstructured":"Updated version of LIP research report 2000-38"},{"key":"24_CR4","doi-asserted-by":"crossref","unstructured":"Defour, D., de Dinechin, F., Muller, J.M.: A new scheme for table-based evaluation of functions. In: 36th Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California (November 2002)","DOI":"10.1109\/ACSSC.2002.1197049"},{"key":"24_CR5","doi-asserted-by":"crossref","unstructured":"Detrey, J., de Dinechin, F.: A VHDL library of LNS operators. In: 37th Asilomar Conference on Signals, Pacific Grove, USA (October 2003)","DOI":"10.1109\/ACSSC.2003.1292376"},{"key":"24_CR6","doi-asserted-by":"crossref","first-page":"10","DOI":"10.1109\/ARITH.1995.465382","volume-title":"12th IEEE Symposium on Computer Arithmetic","author":"H. Hassler","year":"1995","unstructured":"Hassler, H., Takagi, N.: Function evaluation by table look-up and addition. In: Knowles, S., McAllister, W.H. (eds.) 12th IEEE Symposium on Computer Arithmetic, Bath, UK, pp. 10\u201316. IEEE Computer Society Press, Los Alamitos (1995)"},{"key":"24_CR7","doi-asserted-by":"crossref","unstructured":"Lee, D.-U., Luk, W., Villasenor, J., Cheung, P.: Hierarchical segmentation schemes for function evaluation. In: IEEE Conference on Field-Programmable Technology, Tokyo (December 2003)","DOI":"10.1109\/FPT.2003.1275736"},{"issue":"8","key":"24_CR8","doi-asserted-by":"publisher","first-page":"974","DOI":"10.1109\/12.295859","volume":"43","author":"D.M. Lewis","year":"1994","unstructured":"Lewis, D.M.: Interleaved memory function interpolators with application to an accurate LNS arithmetic unit. IEEE Transactions on Computers\u00a043(8), 974\u2013982 (1994)","journal-title":"IEEE Transactions on Computers"},{"key":"24_CR9","unstructured":"Liddicoat, A.A.: High-performance arithmetic for division and the elementary functions. PhD thesis, Stanford University (2002)"},{"key":"24_CR10","doi-asserted-by":"crossref","unstructured":"Mencer, O., Boullis, N., Luk, W., Styles, H.: Parametrized function evaluation on fpgas. In: Field-Programmable Logic and Applications, Belfast (September 2001)","DOI":"10.1007\/3-540-44687-7_56"},{"key":"24_CR11","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4757-2646-6","volume-title":"Elementary Functions, Algorithms and Implementation","author":"J.M. Muller","year":"1997","unstructured":"Muller, J.M.: Elementary Functions, Algorithms and Implementation. Birkhauser, Boston (1997)"},{"issue":"3","key":"24_CR12","doi-asserted-by":"publisher","first-page":"279","DOI":"10.1023\/A:1009984523264","volume":"5","author":"J.M. Muller","year":"1999","unstructured":"Muller, J.M.: A few results on table-based methods. Reliable Computing\u00a05(3), 279\u2013288 (1999)","journal-title":"Reliable Computing"},{"key":"24_CR13","doi-asserted-by":"crossref","unstructured":"Pi\u00f1eiro, J.A., Bruguera, J.D., Muller, J.-M.: Faithful powering computation using table look-up and a fused accumulation tree. In: Burgess, N., Ciminiera, L. (eds.) 15th IEEE Symposium on Computer Arithmetic, Vail, Colorado, June 2001, pp. 40\u201347 (2001)","DOI":"10.1109\/ARITH.2001.930102"},{"issue":"2","key":"24_CR14","doi-asserted-by":"publisher","first-page":"167","DOI":"10.1023\/A:1008004523235","volume":"21","author":"J.E. Stine","year":"1999","unstructured":"Stine, J.E., Schulte, M.J.: The symmetric table addition method for accurate function approximation. Journal of VLSI Signal Processing\u00a021(2), 167\u2013177 (1999)","journal-title":"Journal of VLSI Signal Processing"},{"issue":"6","key":"24_CR15","doi-asserted-by":"publisher","first-page":"1438","DOI":"10.1109\/72.883475","volume":"11","author":"S. Vassiliadis","year":"2000","unstructured":"Vassiliadis, S., Zhang, M., Delgado-Frias, J.G.: Elementary function generators for neural-network emulators. IEEE transactions on neural networks\u00a011(6), 1438\u20131449 (2000)","journal-title":"IEEE transactions on neural networks"}],"container-title":["Lecture Notes in Computer Science","Field Programmable Logic and Application"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-30117-2_24","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,25]],"date-time":"2025-02-25T22:30:33Z","timestamp":1740522633000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-30117-2_24"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2004]]},"ISBN":["9783540229896","9783540301172"],"references-count":16,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-30117-2_24","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2004]]}}}