{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,25]],"date-time":"2025-02-25T23:10:01Z","timestamp":1740525001479,"version":"3.38.0"},"publisher-location":"Berlin, Heidelberg","reference-count":35,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540231769"},{"type":"electronic","value":"9783540301387"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2004]]},"DOI":"10.1007\/978-3-540-30138-7_5","type":"book-chapter","created":{"date-parts":[[2010,9,19]],"date-time":"2010-09-19T00:10:34Z","timestamp":1284855034000},"page":"45-59","source":"Crossref","is-referenced-by-count":4,"title":["A Highly Fault Detectable Cache Architecture for Dependable Computing"],"prefix":"10.1007","author":[{"given":"Hamid R.","family":"Zarandi","sequence":"first","affiliation":[]},{"given":"Seyed Ghassem","family":"Miremadi","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"issue":"4","key":"5_CR1","doi-asserted-by":"publisher","first-page":"393","DOI":"10.1145\/48012.48037","volume":"6","author":"A. Agarwal","year":"1988","unstructured":"Agarwal, A., Hennessy, J., Horowitz, M.: Cache Performance of Operating Systems and Multiprogramming. ACM Trans. Computer Systems\u00a06(4), 393\u2013431 (1988)","journal-title":"ACM Trans. Computer Systems"},{"doi-asserted-by":"crossref","unstructured":"Agarwal, A., Pudar, S.D.: Column-Associative Caches: a Technique for Reducing the Miss Rate of Direct-Mapped Caches. In: Int\u2019l Symp. on Computer Architecture, pp. 179\u2013190 (1993)","key":"5_CR2","DOI":"10.1145\/165123.165153"},{"unstructured":"ARM Company: ARM920T Technical Reference Manual, http:\/\/www.arm.com","key":"5_CR3"},{"doi-asserted-by":"crossref","unstructured":"Asadi, G., Miremadi, S.G., Zarandi, H.R., Ejlali, A.R.: Evaluation of Fault-Tolerant Designs Implemented on SRAM-based FPGAs. In: Proc. IEEE\/IFIP Pacific Rim International Symposium on Dependable Computing, French, pp. 327\u2013333 (2004)","key":"5_CR4","DOI":"10.1109\/PRDC.2004.1276583"},{"doi-asserted-by":"crossref","unstructured":"Bertozzi, D., Benini, L., De Micheli, G.: Low Power Error Resilient Encoding for On-chip Data Buses. In: Proc. of Design, Automation and Test in Europe Conference, France, pp. 102\u2013109 (2002)","key":"5_CR5","DOI":"10.1109\/DATE.2002.998256"},{"unstructured":"Brigham Young University: BYU Cache Simulator, http:\/\/tds.cs.byu.edu","key":"5_CR6"},{"doi-asserted-by":"crossref","unstructured":"Calder, B., Grunwald, D.: Predictive Sequential Associative Cache. In: Proc. 2nd Int\u2019l Symp. High performance Computer Architecture, pp. 244\u2013253 (1996)","key":"5_CR7","DOI":"10.1109\/HPCA.1996.501190"},{"unstructured":"Chen, H., Chiang, J.: Design of an Adjustable-way Set-Associative Cache. In: Proc. Pacific Rim Communications, Computers and signal Processing, pp. 315\u2013318 (2001)","key":"5_CR8"},{"issue":"3","key":"5_CR9","doi-asserted-by":"publisher","first-page":"257","DOI":"10.1109\/12.210168","volume":"42","author":"A. Faridpour","year":"1993","unstructured":"Faridpour, A., Hill, M.: Performance Implications of Tolerating Cache Faults. IEEE Trans. on Computers\u00a042(3), 257\u2013267 (1993)","journal-title":"IEEE Trans. on Computers"},{"doi-asserted-by":"crossref","unstructured":"Farooqui, A.A., Oklobdzija, V.G., Sait, S.M.: Area-Time Optimal Adder with Relative Placement Generator. In: Proc. of Int. Symp. on Circuits and Systems, vol.\u00a05, pp. 141\u2013144 (2003)","key":"5_CR10","DOI":"10.1109\/ISCAS.2003.1206211"},{"key":"5_CR11","volume-title":"Computer architecture Quantitative Approach","author":"J.L. Hennessy","year":"1996","unstructured":"Hennessy, J.L., Patterson, D.A.: Computer architecture Quantitative Approach, 2nd edn. Morgan-Kaufmann Publishing Co., San Francisco (1996)","edition":"2"},{"unstructured":"Hitachi Company: SH4 Embedded Processor, http:\/\/www.hitachi.com","key":"5_CR12"},{"key":"5_CR13","volume-title":"Essentials of Error-Control Coding Techniques","author":"H. Imai","year":"1990","unstructured":"Imai, H.: Essentials of Error-Control Coding Techniques. Academic Press, San Diego (1990)"},{"doi-asserted-by":"crossref","unstructured":"Kamble, M.B., Ghose, K.: Analytical Energy Dissipation Models for Low Power Caches. In: Proc. of Intl. Symp. on Low Power Electronics and Design, pp. 143\u2013148 (1997)","key":"5_CR14","DOI":"10.1145\/263272.263310"},{"doi-asserted-by":"crossref","unstructured":"Kamble, M.B., Ghose, K.: Energy-Efficiency of VLSI Cache: A Comparative Study. In: Proc. IEEE 10th Int\u2019l. Conf. on VLSI Design, pp. 261\u2013267 (1997)","key":"5_CR15","DOI":"10.1109\/ICVD.1997.568087"},{"key":"5_CR16","doi-asserted-by":"publisher","first-page":"8","DOI":"10.1109\/40.259894","volume":"14","author":"J. Karlsson","year":"1994","unstructured":"Karlsson, J., Liden, P., Dahlgern, P., Johansson, R., Gunneflo, U.: Using Heavy-Ion Radiation to Validate Fault-Handling Mechanisms. IEEE Micro.\u00a014, 8\u201323 (1994)","journal-title":"IEEE Micro."},{"doi-asserted-by":"crossref","unstructured":"Kessler, R.R., et al.: Inexpensive Implementations of Associativity. In: Proc. Intl. Symp. Computer Architecture, pp. 131\u2013139 (1989)","key":"5_CR17","DOI":"10.1145\/74926.74941"},{"doi-asserted-by":"crossref","unstructured":"Kim, S., Somani, A.: Area Efficient Architectures for Information Integrity Checking in the Cache Memories. In: Proc. Intl. Symp. Computer Architecture, pp. 246\u2013256 (1999)","key":"5_CR18","DOI":"10.1145\/307338.301000"},{"key":"5_CR19","first-page":"1452","volume":"46","author":"J.H. Lee","year":"2000","unstructured":"Lee, J.H., Lee, J.S., Kim, S.D.: A New Cache Architecture based on Temporal and Spatial Locality. Journal of Systems Architecture\u00a046, 1452\u20131467 (2000)","journal-title":"Journal of Systems Architecture"},{"key":"5_CR20","doi-asserted-by":"publisher","first-page":"441","DOI":"10.1109\/24.406580","volume":"44","author":"G. Miremadi","year":"1995","unstructured":"Miremadi, G., Torin, J.: Evaluating Processor-Behavior and Three Error-Detection Mechanisms Using Physical Fault Injection. IEEE Trans. Reliability\u00a044, 441\u2013453 (1995)","journal-title":"IEEE Trans. Reliability"},{"key":"5_CR21","doi-asserted-by":"publisher","first-page":"98","DOI":"10.1109\/4.68123","volume":"26","author":"J.M. Mulder","year":"1991","unstructured":"Mulder, J.M., Quach, N.T., Flynn, M.J.: An Area Model for On-Chip Memories and its Applications. IEEE Journal of Solid State Circuits\u00a026, 98\u2013106 (1991)","journal-title":"IEEE Journal of Solid State Circuits"},{"doi-asserted-by":"crossref","unstructured":"Ranganathan, P., Adve, S., Jouppi, N.P.: Reconfigurable Caches and their Application to Media Processing. In: Proc. Int. Symp. Computer Architecture, pp. 214\u2013224 (2000)","key":"5_CR22","DOI":"10.1145\/339647.339685"},{"doi-asserted-by":"crossref","unstructured":"Seznec, A.: A Case for Two-Way Skewed-Associative Caches. In: Proc. Intl. Symp. Computer Architecture, pp. 169\u2013178 (1993)","key":"5_CR23","DOI":"10.1145\/165123.165152"},{"doi-asserted-by":"crossref","unstructured":"Shirvani, P., McCuskey, E.J.: PADded Cache: A New Fault-Tolerance Technique for Cache Memories. In: Proc. 17th IEEE VLSI Test Symp., pp. 440\u2013445 (1999)","key":"5_CR24","DOI":"10.1109\/VTEST.1999.766701"},{"issue":"4","key":"5_CR25","doi-asserted-by":"publisher","first-page":"473","DOI":"10.1145\/356887.356892","volume":"14","author":"A.J. Smith","year":"1982","unstructured":"Smith, A.J.: Cache memories. Computing Survey\u00a014(4), 473\u2013530 (1982)","journal-title":"Computing Survey"},{"unstructured":"Intel Corporation: Pentium\u00ae Family Developer\u2019s Manual, http:\/\/www.intel.com","key":"5_CR26"},{"doi-asserted-by":"crossref","unstructured":"Reed, R.: Heavy Ion and Proton Induced Single Event Multiple Upsets. In: IEEE Nuclear and Space Radiation Effects Conference (1997)","key":"5_CR27","DOI":"10.1109\/23.659039"},{"unstructured":"Swazey, P.: SRAM Organization, Control, and Speed, and Their Effect on Cache Memory Design. In: Midcon 1987, pp. 434\u2013437 (1987)","key":"5_CR28"},{"unstructured":"Wilton, S.J.E., Jouppi, N.P.: An Enhanced Access and Cycle Time Model for On-chip Caches. Digital WRL Research Report 93\/5 (1994)","key":"5_CR29"},{"doi-asserted-by":"crossref","unstructured":"Wu, A., Meador, J.: Fast, Area-Efficient CMOS Parity Generation. In: Proc. 33rd Midwest Symposium on Circuits and Systems, pp. 874\u2013876 (1990)","key":"5_CR30","DOI":"10.1109\/MWSCAS.1990.140860"},{"key":"5_CR31","doi-asserted-by":"publisher","first-page":"677","DOI":"10.1109\/4.509850","volume":"31","author":"S.J.E. Wilton","year":"1996","unstructured":"Wilton, S.J.E., Jouppi, N.P.: CACTI: An Enhancement Cache Access and Cycle Time Model. IEEE Journal of Solid-State Circuits\u00a031, 677\u2013688 (1996)","journal-title":"IEEE Journal of Solid-State Circuits"},{"doi-asserted-by":"crossref","unstructured":"Zhang, W., Gurumurthi, S., Kandemir, M., Sivasubramaniam, A.: ICR: In-Cache Replication for Enhancing Data Cache Reliability. In: Proceedings of the International Conference on Dependable Systems and Networks (DSN), pp. 291\u2013300 (2003)","key":"5_CR32","DOI":"10.1109\/DSN.2003.1209939"},{"doi-asserted-by":"crossref","unstructured":"Zhang, C., Vahid, F., Najjar, W.: A Highly Configurable Cache Architecture for Embedded Systems. In: Int. Symp. on Computer Architecture, pp. 136\u2013146 (2003)","key":"5_CR33","DOI":"10.1145\/859618.859635"},{"doi-asserted-by":"crossref","unstructured":"Zhang, C., Zhang, X., Yan, Y.: Two Fast and High-Associativity Cache Schemes. IEEE Micro., 40\u201349 (1997)","key":"5_CR34","DOI":"10.1109\/40.621212"},{"unstructured":"Standard Performance Evaluation Corporation: SPEC CPU 2000 (2000), benchmarks, http:\/\/www.specbench.org\/osg\/cpu2000","key":"5_CR35"}],"container-title":["Lecture Notes in Computer Science","Computer Safety, Reliability, and Security"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-30138-7_5.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,25]],"date-time":"2025-02-25T22:36:53Z","timestamp":1740523013000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-30138-7_5"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2004]]},"ISBN":["9783540231769","9783540301387"],"references-count":35,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-30138-7_5","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2004]]}}}