{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,26]],"date-time":"2025-02-26T05:33:42Z","timestamp":1740548022105,"version":"3.38.0"},"publisher-location":"Berlin, Heidelberg","reference-count":16,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540230953"},{"type":"electronic","value":"9783540302056"}],"license":[{"start":{"date-parts":[[2004,1,1]],"date-time":"2004-01-01T00:00:00Z","timestamp":1072915200000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2004]]},"DOI":"10.1007\/978-3-540-30205-6_17","type":"book-chapter","created":{"date-parts":[[2010,9,21]],"date-time":"2010-09-21T21:00:42Z","timestamp":1285102842000},"page":"148-158","source":"Crossref","is-referenced-by-count":19,"title":["Sleepy Stack Reduction of Leakage Power"],"prefix":"10.1007","author":[{"given":"Jun Cheol","family":"Park","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"suffix":"III","given":"Vincent J.","family":"Mooney","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Philipp","family":"Pfeiffenberger","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"issue":"12","key":"17_CR1","doi-asserted-by":"crossref","first-page":"68","DOI":"10.1109\/MC.2003.1250885","volume":"36","author":"N.S. Kim","year":"2003","unstructured":"Kim, N.S., et al.: Leakage Current: Moore\u2019s Law Meets Static Power. IEEE Computer\u00a036(12), 68\u201375 (2003)","journal-title":"IEEE Computer"},{"key":"17_CR2","unstructured":"International Technology Roadmap for Semiconductors by Semiconductor Industry Association (2002), http:\/\/public.itrs.net"},{"issue":"11","key":"17_CR3","doi-asserted-by":"publisher","first-page":"1599","DOI":"10.1109\/4.962279","volume":"36","author":"L.T. Clark","year":"2001","unstructured":"Clark, L.T., et al.: An Embedded 32-b Microprocessor Core for Low-Power and High-Performance Applications. IEEE Journal of Solid-State Circuits\u00a036(11), 1599\u20131608 (2001)","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"17_CR4","doi-asserted-by":"crossref","unstructured":"Powell, M., Yang, S.-H., Falsafi, B., Roy, K., Vijaykumar, T.N.: Gated-Vdd: A Circuit Technique to Reduce Leakage in Deep-submicron Cache Memories. In: International Symposium on Low Power Electronics and Design, July 2000, pp. 90\u201395 (2000)","DOI":"10.1145\/344166.344526"},{"issue":"8","key":"17_CR5","doi-asserted-by":"publisher","first-page":"847","DOI":"10.1109\/4.400426","volume":"30","author":"S. Mutoh","year":"1995","unstructured":"Mutoh, S., et al.: 1-V Power Supply High-speed Digital Circuit Technology with Multithreshold-Voltage CMOS. IEEE Journal of Solis-State Circuits\u00a030(8), 847\u2013854 (1995)","journal-title":"IEEE Journal of Solis-State Circuits"},{"key":"17_CR6","doi-asserted-by":"crossref","unstructured":"Chen, Z., Johnson, M., Wei, L., Roy, K.: Estimation of Standby Leakage Power in CMOS Circuits Considering Accurate Modeling of Transistor Stacks. In: International Symposium on Low Power Electronics and Design, pp. 239\u2013244 (1998)","DOI":"10.1145\/280756.280917"},{"key":"17_CR7","doi-asserted-by":"crossref","unstructured":"Narendra, S., Borkar, S., De, V., Antoniadis, D., Chandrakasan, A.: Scaling of Stack Effect and its Application for Leakage Reduction. In: International Symposium on Low Power Electronics and Design, August 2001, pp. 195\u2013200 (2001)","DOI":"10.1145\/383082.383132"},{"issue":"1","key":"17_CR8","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1109\/92.988724","volume":"10","author":"M. Johnson","year":"2002","unstructured":"Johnson, M., Somasekhar, D., Chiou, L.-Y., Roy, K.: Leakage Control with Efficient Use of Transistor Stacks in Single Threshold CMOS. IEEE Transactions on VLSI Systems\u00a010(1), 1\u20135 (2002)","journal-title":"IEEE Transactions on VLSI Systems"},{"key":"17_CR9","doi-asserted-by":"crossref","unstructured":"Min, K.-S., Kawaguchi, H., Sakurai, T.: Zigzag Super Cut-off CMOS (ZSCCMOS) Block Activation with Self-Adaptive Voltage Level Controller: An Alternative to Clock-gating Scheme in Leakage Dominant Era. In: IEEE International Solid-State Circuits Conference, February 2003, vol.\u00a01, pp. 400\u2013401 (2003)","DOI":"10.1109\/ISSCC.2003.1234355"},{"key":"17_CR10","doi-asserted-by":"crossref","unstructured":"Flautner, K., Kim, N.S., Martin, S., Blaauw, D., Mudge, T.: Drowsy Caches: Simple Techniques for Reducing Leakage Power. In: International Symposium on Computer Architecture, May 2002, pp. 148\u2013157 (2002)","DOI":"10.1145\/545214.545232"},{"key":"17_CR11","unstructured":"Avant! Corporation, http:\/\/www.avanticorp.com"},{"key":"17_CR12","unstructured":"Cadence Design Systems, http:\/\/www.cadence.com"},{"key":"17_CR13","unstructured":"NC State University Cadence Tool Information, http:\/\/www.cadence.ncsu.edu"},{"key":"17_CR14","unstructured":"Berkeley Predictive Technology Model (BPTM), http:\/\/www-device.eecs.berkeley.edu\/~ptm\/"},{"key":"17_CR15","doi-asserted-by":"crossref","unstructured":"Cao, Y., Sato, T., Sylvester, D., Orshansky, M., Hu, C.: New paradigm of predictive MOSFET and interconnect modeling for early circuit design. In: Proc. of IEEE CICC, June 2000, pp. 201\u2013204 (2000)","DOI":"10.1109\/CICC.2000.852648"},{"key":"17_CR16","unstructured":"Pfeiffenberger, P., Park, J., Mooney, V.: Some Layouts Using the Sleepy Stack Approach. Technical Report GIT-CC-04-05, Georgia Institute of Technology (June 2004), http:\/\/www.cc.gatech.edu\/tech_reports\/index.04.html"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-30205-6_17","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,25]],"date-time":"2025-02-25T23:49:21Z","timestamp":1740527361000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-30205-6_17"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2004]]},"ISBN":["9783540230953","9783540302056"],"references-count":16,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-30205-6_17","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2004]]}}}