{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T20:03:32Z","timestamp":1725566612582},"publisher-location":"Berlin, Heidelberg","reference-count":24,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540230953"},{"type":"electronic","value":"9783540302056"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2004]]},"DOI":"10.1007\/978-3-540-30205-6_31","type":"book-chapter","created":{"date-parts":[[2010,9,21]],"date-time":"2010-09-21T21:00:42Z","timestamp":1285102842000},"page":"289-300","source":"Crossref","is-referenced-by-count":1,"title":["Minimizing the Power Consumption of an Asynchronous Multiplier"],"prefix":"10.1007","author":[{"given":"Yijun","family":"Liu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Steve","family":"Furber","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"volume-title":"Designing CMOS Circuits for Low Power","year":"2002","key":"31_CR1","unstructured":"Soudris, D., Piguet, C., Goutis, C. (eds.): Designing CMOS Circuits for Low Power. Kluwer Academic Publishers, Dordrecht (2002)"},{"key":"31_CR2","volume-title":"Low power CMOS Design","author":"T. Callaway","year":"1998","unstructured":"Callaway, T., Swartzlander, E.: The Power Consumption of CMOS Adders and Multipliers. In: Chandrakasan, A., Brodersen, R. (eds.) Low power CMOS Design, IEEE Press, Los Alamitos (1998)"},{"key":"31_CR3","doi-asserted-by":"crossref","unstructured":"Bisdounis, L., Gouvetas, D., Koufopavlou, O.: Circuit Techniques for Reducing Power Consumption in Adders and Multipliers. In: [1]","DOI":"10.1007\/978-1-4757-3530-7_5"},{"key":"31_CR4","doi-asserted-by":"crossref","unstructured":"Fried, R.: Minimizing Energy Dissipation in High-Speed Multipliers. In: International Symposium on Low Power Electronics and Design (1997)","DOI":"10.1145\/263272.263337"},{"issue":"part 2","key":"31_CR5","doi-asserted-by":"publisher","first-page":"236","DOI":"10.1093\/qjmam\/4.2.236","volume":"4","author":"A.D. Booth","year":"1951","unstructured":"Booth, A.D.: A Signed Binary Multiplication Technique. Quarterly J. Mech. Appl. Math.\u00a04(part 2), 236\u2013240 (1951)","journal-title":"Quarterly J. Mech. Appl. Math."},{"key":"31_CR6","unstructured":"Shen, N.-Y., Chen, O.T.-C.: Low power multipliers by minimizing switching activities of partial products. In: IEEE International Symposium on Circuits and Systems, May 26-29, vol.\u00a04 (2002)"},{"key":"31_CR7","unstructured":"Gu, J., Chang, C.-H.: Ultra low voltage, low power 4-2 compressor for high speed multiplications. In: International Symposium on Circuits and Systems 2003, May 25-28, vol.\u00a05, pp. 4\u20132 (2003)"},{"key":"31_CR8","doi-asserted-by":"crossref","unstructured":"Hsiao, S.-F., Jiang, M.-R., Yeh, J.-S.: Design of high-speed low-power 3-2 counter and 4-2 compressor for fast multipliers. Electronics Letters\u00a034(4) (February19, 1998)","DOI":"10.1049\/el:19980306"},{"key":"31_CR9","doi-asserted-by":"crossref","unstructured":"Prasad, K., Parhi, K.K.: Low-power 4-2 and 5-2 compressors. In: Conference Record of the Thirty-Fifth Asilomar Conference on Signals, Systems and Computers, November 4-7, vol.\u00a01 (2001)","DOI":"10.1109\/ACSSC.2001.986892"},{"issue":"7","key":"31_CR10","doi-asserted-by":"publisher","first-page":"1079","DOI":"10.1109\/4.597298","volume":"32","author":"R. Zimmermann","year":"1997","unstructured":"Zimmermann, R., Fichtner, W.: Low-Power Logic Styles: CMOS versus Pass- Transistor Logic. IEEE Journal Of Solid State Circuits\u00a032(7), 1079\u20131090 (1997)","journal-title":"IEEE Journal Of Solid State Circuits"},{"key":"31_CR11","unstructured":"Liu, J.: Arithmetic and Control Components for an Asynchronous System, PhD thesis, The University of Manchester (1997)"},{"key":"31_CR12","doi-asserted-by":"crossref","unstructured":"Furber, S.B., Edwards, D.A., Garside, J.D.: AMULET3: a 100 MIPS Asynchronous Embedded Processor. In: IEEE International Conference on Computer Design, September 17-20 (2000)","DOI":"10.1109\/ICCD.2000.878304"},{"issue":"2","key":"31_CR13","doi-asserted-by":"publisher","first-page":"247","DOI":"10.1109\/92.502196","volume":"4","author":"S.B. Furber","year":"1996","unstructured":"Furber, S.B., Day, P.: Four-Phase Micropipeline Latch Control Circuits. IEEE Transactions on VLSI Systems\u00a04(2), 247\u2013253 (1996)","journal-title":"IEEE Transactions on VLSI Systems"},{"key":"31_CR14","doi-asserted-by":"crossref","unstructured":"Furber, S.B., Efthymiou, A., Garside, J.D., Lewis, M.J.G., Lloyd, D.W., Temple, S.: Power Management in the AMULET Microprocessors. IEEE Design and Test of Computers Journal special issue, 42\u201352 (March-April 2001) (Macii, E. ed.)","DOI":"10.1109\/54.914617"},{"volume-title":"Principles of Asynchronous Circuit Design: A systems perspective","year":"2001","key":"31_CR15","unstructured":"Spars\u00f8, J., Furber, S. (eds.): Principles of Asynchronous Circuit Design: A systems perspective. Kluwer Academic Publishers, Dordrecht (2001)"},{"key":"31_CR16","doi-asserted-by":"crossref","unstructured":"Lewis, M., Garside, J.D., Brackenbury, L.E.M.: Reconfigurable Latch Controllers for Low Power Asynchronous Circuits. In: Internation Symposium on Advanced Research in Asynchronous Circuits and Systems (April 1999)","DOI":"10.1109\/ASYNC.1999.761520"},{"key":"31_CR17","doi-asserted-by":"crossref","unstructured":"Riocreux, P.A., Lewis, M.J.G., Brackenbury, L.E.M.: Power reduction in self-timed circuits using early-open latch controllers. Electronics Letters\u00a036(2) (January 20, 2000)","DOI":"10.1049\/el:20000178"},{"key":"31_CR18","doi-asserted-by":"crossref","unstructured":"Liu, Y., Furber, S.B.: The Design of a Low Power Asynchronous Multiplier. In: International Symposium on Low Power Electronics and Design, Newport Beach, California, USA, August 9-11 (2004)","DOI":"10.1145\/1013235.1013310"},{"key":"31_CR19","doi-asserted-by":"crossref","unstructured":"Landman, P.E., Rabaey, J.M.: Architectural power analysis: The dual bit type method. IEEE Transactions on Very Large Scale Integration (VLSI) Systems\u00a03(2) (June 1995)","DOI":"10.1109\/92.386219"},{"key":"31_CR20","unstructured":"Zyuban, V., Kogge, P.: Split Register File Architectures for Inherently Low Power Microprocessor. In: Power Driven Microarchitecture Workshop at ISC 1998 (June 1998)"},{"key":"31_CR21","doi-asserted-by":"crossref","unstructured":"Pasternak, J.H., Salama, C.A.T.: Differential pass-transistor logic. Circuits and Devices Magazine, IEEE\u00a09(4) (July 1993)","DOI":"10.1109\/101.250230"},{"key":"31_CR22","doi-asserted-by":"crossref","unstructured":"Suzuki, M., Ohkubo, N., Yamanaka, T., Shimizu, A., Sasaki, K.: A 1.5 ns 32 b CMOS ALU in double pass-transistor logic. In: IEEE International Conference on Solid-State Circuits, 40th ISSCC, February 24-26 (1993)","DOI":"10.1109\/ISSCC.1993.280071"},{"key":"31_CR23","unstructured":"Yuan, J., Svensson, C.: New TSPC latches and flipflops minimizing delay and power. In: IEEE International Symposium on VLSI Circuits, Digest of Technical Papers, June 13-15 (1996)"},{"key":"31_CR24","doi-asserted-by":"publisher","first-page":"1440","DOI":"10.1109\/4.340417","volume":"29","author":"G. Gerosa","year":"1994","unstructured":"Gerosa, G., Gary, S., Dietz, C., Dac, P., Hoover, K., Alvarez, J., Sanchez, H., Ippolito, P., Tai, N., Litch, S., Eno, J., Golab, J., Vanderschaaf, N., Kahle, J.: A 2.2 W, 80 MHz superscalar RISC microprocessor. IEEE Journal on Solid-State Circuits\u00a029, 1440\u20131452 (1994)","journal-title":"IEEE Journal on Solid-State Circuits"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-30205-6_31.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,11,19]],"date-time":"2020-11-19T04:48:16Z","timestamp":1605761296000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-30205-6_31"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2004]]},"ISBN":["9783540230953","9783540302056"],"references-count":24,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-30205-6_31","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2004]]}}}