{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,26]],"date-time":"2025-02-26T05:33:58Z","timestamp":1740548038989,"version":"3.38.0"},"publisher-location":"Berlin, Heidelberg","reference-count":4,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540230953"},{"type":"electronic","value":"9783540302056"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2004]]},"DOI":"10.1007\/978-3-540-30205-6_39","type":"book-chapter","created":{"date-parts":[[2010,9,21]],"date-time":"2010-09-21T21:00:42Z","timestamp":1285102842000},"page":"372-380","source":"Crossref","is-referenced-by-count":0,"title":["A 260ps Quasi-static ALU in 90nm CMOS"],"prefix":"10.1007","author":[{"given":"F.","family":"Pessolano","sequence":"first","affiliation":[]},{"given":"R. I. M. P.","family":"Meijer","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"doi-asserted-by":"crossref","unstructured":"Han, T., Carlson, D.A.: Fast Area Efficient VLSI Adders. In: 8th Symposium on Computer Arithmetic, May 1987, pp. 49\u201356 (1987)","key":"39_CR1","DOI":"10.1109\/ARITH.1987.6158699"},{"doi-asserted-by":"crossref","unstructured":"Bai, X., et al.: Uncertainty-aware circuit tuning. In: Proc. of 39th Design Automation Conference, New Orleans (June 2002)","key":"39_CR2","DOI":"10.1145\/513918.513935"},{"issue":"8","key":"39_CR3","doi-asserted-by":"publisher","first-page":"786","DOI":"10.1109\/TC.1973.5009159","volume":"22","author":"P.M. Kogge","year":"1973","unstructured":"Kogge, P.M., Stone, H.S.: A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations. IEEE Transactions on Computers\u00a022(8), 786\u2013793 (1973)","journal-title":"IEEE Transactions on Computers"},{"doi-asserted-by":"crossref","unstructured":"Anders, M., et al.: A 6.5GHz 130nm Single-Ended Dynamic ALU and Instruction- Scheduler Loop. In: ISSCC Digest of Technical Papers, February 2002, pp. 410\u2013477 (2002)","key":"39_CR4","DOI":"10.1109\/ISSCC.2002.993106"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-30205-6_39.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,25]],"date-time":"2025-02-25T23:48:38Z","timestamp":1740527318000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-30205-6_39"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2004]]},"ISBN":["9783540230953","9783540302056"],"references-count":4,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-30205-6_39","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2004]]}}}