{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T12:08:44Z","timestamp":1759147724294,"version":"3.38.0"},"publisher-location":"Berlin, Heidelberg","reference-count":18,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540230953"},{"type":"electronic","value":"9783540302056"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2004]]},"DOI":"10.1007\/978-3-540-30205-6_45","type":"book-chapter","created":{"date-parts":[[2010,9,21]],"date-time":"2010-09-21T21:00:42Z","timestamp":1285102842000},"page":"433-441","source":"Crossref","is-referenced-by-count":1,"title":["Simultaneous Wire Sizing and Decoupling Capacitance Budgeting for Robust On-Chip Power Delivery"],"prefix":"10.1007","author":[{"given":"Jingjing","family":"Fu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zuying","family":"Luo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xianlong","family":"Hong","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yici","family":"Cai","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sheldon X. -D.","family":"Tan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhu","family":"Pan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"45_CR1","doi-asserted-by":"crossref","unstructured":"Chen, H.H., Ling, D.D.: Power supply noise analysis methodology for deep-submicron VLSI chip design. In: Proc. 34th ACM\/IEEE Design Automation Conf., pp. 638\u2013643 (1997)","DOI":"10.1109\/DAC.1997.597223"},{"key":"45_CR2","doi-asserted-by":"crossref","unstructured":"Bai, G., Bobba, S., Hajj, I.N.: Simulation and optimization of the power distribution network in VLSI circuits. In: Proc. IEEE\/ACM International Conf. on Computer-Aided Design, pp. 481\u2013486 (2000)","DOI":"10.1109\/ICCAD.2000.896519"},{"key":"45_CR3","doi-asserted-by":"crossref","unstructured":"Su, H.-H., Gala, K.H., Sapatnekar, S.S.: Fast analysis and optimization of power\/ground networks. In: Proc. IEEE\/ACM International Conf. on Computer-Aided Design, pp. 477\u2013482 (2000)","DOI":"10.1109\/ICCAD.2000.896518"},{"key":"45_CR4","doi-asserted-by":"crossref","unstructured":"Chowdhury, S., Breuer, M.A.: Minimal area design of power\/ground nets having graph topologies. IEEE Trans. on Circuits and Systems, 1441\u20131451 (1987)","DOI":"10.1109\/TCS.1987.1086084"},{"key":"45_CR5","doi-asserted-by":"crossref","unstructured":"Mitsuhashi, T., Kuh, E.S.: Power and Ground Network Topology Optimization for Cell Based VLSIs. In: Proc. 29th ACM\/IEEE Design Automation Conference, pp. 524\u2013529 (1992)","DOI":"10.1109\/DAC.1992.227748"},{"key":"45_CR6","doi-asserted-by":"crossref","unstructured":"Tan, X.-D., Shi, C.-J.: Reliability-constrained area optimization of VLSI power\/ground networks via sequence of linear programming. In: Proc. 36th ACM\/IEEE Design Automation Conf., pp. 78\u201383 (1999)","DOI":"10.1145\/309847.309880"},{"key":"45_CR7","unstructured":"Wu, X.-H., Hong, X.-L., Cai, Y.-C., et al.: Area minimization of power distribution network using efficient nonlinear programming techniques. In: Proc. IEEE\/ACM International Conf. on Computer-Aided Design, pp. 153\u2013157 (2001)"},{"key":"45_CR8","doi-asserted-by":"crossref","unstructured":"Zhao, S.-Y., Roy, K.K., Koh, C.-K.: Decoupling capacitance allocation for power supply noise suppression. In: Proc. IEEE\/ACM International Symp. on Physical Design, pp. 66\u201371 (2001)","DOI":"10.1145\/369691.369737"},{"key":"45_CR9","doi-asserted-by":"crossref","unstructured":"Su, H.-H., Roy, K.K., Sapatnekar, S.S., Nassif, S.R.: An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts. In: Proc. IEEE\/ACM International Symp. on Physical Design, pp. 68\u201375 (2002)","DOI":"10.1145\/505388.505405"},{"key":"45_CR10","doi-asserted-by":"crossref","unstructured":"Wang, K., Marek-Sadowask, M.: On-chip power supply network optimization using multigrid-based technique. In: Proc. ACM\/IEEE Design Automation Conf., June 2003, pp. 113\u2013118 (2003)","DOI":"10.1145\/775832.775864"},{"key":"45_CR11","doi-asserted-by":"crossref","unstructured":"Tan, X.-D., Shi, C.-J.: Fast power-ground network optimization using equivalent circuit modeling. In: Proc. 38th ACM\/IEEE Design Automation Conf., pp. 550\u2013554 (2001)","DOI":"10.1145\/378239.379021"},{"issue":"8","key":"45_CR12","doi-asserted-by":"publisher","first-page":"645","DOI":"10.1109\/43.712097","volume":"17","author":"M. Odabasioglu","year":"1998","unstructured":"Odabasioglu, M.: PRIME: Passive reduction-order interconnect macromodeling algorithm. IEEE Trans. On Computer-Aided Design\u00a017(8), 645\u2013654 (1998)","journal-title":"IEEE Trans. On Computer-Aided Design"},{"key":"45_CR13","doi-asserted-by":"crossref","unstructured":"Dharchoudhury, A., Panda, R., Blaauw, D., Vaidyanathan, R., et al.: Design and analysis of power distribution networks in power PC microprocessors. In: Proc. ACM\/IEEE Design Automation Conf., June 1998, pp. 738\u2013743 (1998)","DOI":"10.1145\/277044.277229"},{"issue":"10","key":"45_CR14","doi-asserted-by":"publisher","first-page":"1148","DOI":"10.1109\/TCAD.2002.802271","volume":"21","author":"J.N. Kozhaya","year":"2002","unstructured":"Kozhaya, J.N., Nassif, S.R., Najm, F.N.: A multigrid-like technique for power grid analysis. IEEE Trans. Computer-Aided Design\u00a021(10), 1148\u20131160 (2002)","journal-title":"IEEE Trans. Computer-Aided Design"},{"key":"45_CR15","doi-asserted-by":"crossref","unstructured":"Zhao, M., Panda, R.V., Sapatnekar, S.S., et al.: Hierarchical analysis of power distribution networks. In: Proc. ACM\/IEEE Design Automation Conf., June 2000, pp. 150\u2013155 (2000)","DOI":"10.1145\/337292.337355"},{"key":"45_CR16","doi-asserted-by":"crossref","unstructured":"Chen, T., Chen, C.C.: Efficient large-scale power grid analysis based on preconditioned Krylov-subspace iterative method. In: Proc. ACM\/IEEE Design Automation Conf., June 2001, pp. 559\u2013562 (2001)","DOI":"10.1145\/378239.379023"},{"key":"45_CR17","doi-asserted-by":"crossref","unstructured":"Nassif, S.R., Kozhaya, J.N.: Fast power grid simulation. In: Proc. ACM\/IEEE Design Automation Conf., June 2000, pp. 156\u2013161 (2000)","DOI":"10.1145\/337292.337359"},{"key":"45_CR18","unstructured":"Fu, J., Luo, Z., Hong, X., Cai, Y., Tan, S.X.-D., Pan, Z.: A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery. In: Proc. Asia South Pacific Design Automation Conf (ASPDAC), January 2004, pp. 505\u2013510 (2004)"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-30205-6_45.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,25]],"date-time":"2025-02-25T23:49:14Z","timestamp":1740527354000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-30205-6_45"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2004]]},"ISBN":["9783540230953","9783540302056"],"references-count":18,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-30205-6_45","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2004]]}}}