{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,10,2]],"date-time":"2026-10-02T08:39:18Z","timestamp":1790930358316,"version":"4.1.0"},"publisher-location":"Berlin, Heidelberg","reference-count":21,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"value":"9783540230953","type":"print"},{"value":"9783540302056","type":"electronic"}],"license":[{"start":{"date-parts":[[2004,1,1]],"date-time":"2004-01-01T00:00:00Z","timestamp":1072915200000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2004]]},"DOI":"10.1007\/978-3-540-30205-6_56","type":"book-chapter","created":{"date-parts":[[2010,9,21]],"date-time":"2010-09-21T21:00:42Z","timestamp":1285102842000},"page":"541-552","source":"Crossref","is-referenced-by-count":4,"title":["Low Effort, High Accuracy Network-on-Chip Power Macro Modeling"],"prefix":"10.1007","author":[{"given":"Andrea","family":"Bona","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Vittorio","family":"Zaccaria","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Roberto","family":"Zafalon","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"297","reference":[{"key":"56_CR1","volume-title":"Interconnection Networks: an Engineering Approach","author":"J. Duato","year":"1997","unstructured":"Duato, J., Yalamanchili, S., Ni, L.: Interconnection Networks: an Engineering Approach. IEEE Computer Society Press, Los Alamitos (1997)"},{"key":"56_CR2","unstructured":"Lahiri, K., Dey, S., et al.: Efficient Exploration of the SOC Communication Architecture Design Space. In: Proc. of ICCAD 2000, S.Jose, USA (November 2000)"},{"key":"56_CR3","doi-asserted-by":"crossref","unstructured":"Dally, W., Toles, B.: Route Packets, not Wires: On-Chip Interconnection Network. In: Proceedings of 38th DAC 2001, Las Vegas, USA (June 2001)","DOI":"10.1145\/378239.379048"},{"key":"56_CR4","unstructured":"Vincentelli, S., Rabaey, J., Keutzer, K., et al.: Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design. In: Proceedings of 38th DAC 2001, Las Vegas, USA (June 2001)"},{"key":"56_CR5","doi-asserted-by":"crossref","unstructured":"Karim, F., Nguyen, A., et al.: On Chip Communication Architecture for OC-768 Network Processors. In: Proceedings of 38th DAC 2001, Las Vegas, USA (June 2001)","DOI":"10.1145\/378239.379047"},{"key":"56_CR6","unstructured":"Lahiri, K., Dey, S., et al.: Evaluation of the Traffic Performance Characteristics of Systemon-Chip Communication Architectures. In: Proc. 14th Int\u2019l Conference on VLSI Design 2001, Los Alamitos, USA (2001)"},{"key":"56_CR7","doi-asserted-by":"crossref","unstructured":"Benini, L., De Micheli, G.: Network on Chip: A New SoC Paradigm. IEEE Computer (January 2002)","DOI":"10.1109\/2.976921"},{"key":"56_CR8","doi-asserted-by":"crossref","unstructured":"Ye, T., Benini, L., De Micheli, G.: Analysis of power consumption on switch fabrics in network routers. In: Proceedings of 39th DAC 2002, New Orleans, USA (June 2002)","DOI":"10.1145\/514049.514051"},{"key":"56_CR9","unstructured":"Kumar, S., et al.: A network on chip architecture and design methodology. In: International Symposium on VLSI 2002 (2002)"},{"key":"56_CR10","unstructured":"Wang, H.-S., Zhu, X., Peh, L.-S., Malik, S.: Orion: A Power-Performance Simulator for Interconnection Networks. In: International Symposium on Microarchitecture, MICRO-35, Istanbul, Turkey (November 2002)"},{"key":"56_CR11","doi-asserted-by":"crossref","unstructured":"Ye, T., De Micheli, G., Benini, L.: Packetized On-Chip Interconnect Communication Analysis for MPSoC. In: Proceedings of DATE 2003, Munich, Germany, March 2003, pp. 344\u2013349 (2003)","DOI":"10.1109\/DATE.2003.1253632"},{"key":"56_CR12","unstructured":"Hu, J., Marculescu, R.: Exploiting the Routing Flexibility for Energy\/Performance Aware Mapping of Regular NoC Architectures. In: Proceedings of DATE 2003, Munich, Germany, March 2003, pp. 688\u2013693 (2003)"},{"key":"56_CR13","volume-title":"System Design with SystemC","author":"T. Grotker","year":"2002","unstructured":"Grotker, T., Liao, S., Martin, G., Swan, S.: System Design with SystemC. Kluwer Academic Publishers, Dordrecht (2002)"},{"key":"56_CR14","unstructured":"STBus Communication System: Concepts and Definitions, Reference Guide, STMicroelectronics (October 2002)"},{"key":"56_CR15","unstructured":"STBus Functional Specs, STMicroelectronics, public web support site, STMicroelectronics (April 2003), http:\/\/www.stmcu.com\/inchtml-pages-STBus_intro.html"},{"key":"56_CR16","unstructured":"Synopsys Inc., Core Consultant Reference Manual, Power Compiler Reference Manual and VCS: Verilog Compiled Simulator Reference Manual, v2003.06 (June 2003)"},{"key":"56_CR17","doi-asserted-by":"crossref","unstructured":"Patel, C., Chai, S., Yalamanchili, S., Schimmel, D.: Power-constrained design of multiprocessor interconnection networks. In: Proc. Int. Conf. Computer Design, October 1997, pp. 408\u2013416 (1997)","DOI":"10.1109\/ICCD.1997.628902"},{"key":"56_CR18","doi-asserted-by":"crossref","unstructured":"Zimmermann, H.: OSI Reference Model \u2013 The ISO model of architecture for Open System Interconnection. IEEE Trans. on Communication\u00a0(4) (April 1980)","DOI":"10.1109\/TCOM.1980.1094702"},{"key":"56_CR19","unstructured":"VSI Alliance Standard, System-Level Interface Behavioral Documentation Standard Version 1 (released March 2000)"},{"key":"56_CR20","volume-title":"Empirical model-building and response surfaces","author":"G.E.P. Box","year":"1987","unstructured":"Box, G.E.P., Richard, D.N.: Empirical model-building and response surfaces. John Wiley & Sons, New York (1987)"},{"key":"56_CR21","unstructured":"Bona, Zaccaria, V., Zafalon, R.: System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip. In: IEEE DATE 2004, Paris, France (February 2004)"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-30205-6_56","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,25]],"date-time":"2025-02-25T23:49:18Z","timestamp":1740527358000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-30205-6_56"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2004]]},"ISBN":["9783540230953","9783540302056"],"references-count":21,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-30205-6_56","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"value":"0302-9743","type":"print"},{"value":"1611-3349","type":"electronic"}],"subject":[],"published":{"date-parts":[[2004]]}}}